Lines Matching refs:lane

513    least significant lane (rightmost in the register).  */
7056 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
7091 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
7156 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
7199 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
7779 values (aa,bb), computes, for each lane:
7818 value aa, computes, for each lane
8522 assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) );
8533 assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) );
8865 put it into the specified lane of mmx(G). */
8868 mmx reg. t4 is the new lane value. t5 is the original
8870 Int lane;
8883 lane = insn[3+1-1];
8884 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
8890 lane = insn[3+alen-1];
8892 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
8897 switch (lane & 3) {
9163 putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
9170 putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
9186 1/*upper lane*/ ) );
9201 0/*lower lane*/,
9208 putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/,
9224 0/*lower lane*/ ) );
9587 assign( argR, getXMMRegLane64F( eregOfRM(modrm), 0/*lowest lane*/ ) );
9598 assign( argL, getXMMRegLane64F( gregOfRM(modrm), 0/*lowest lane*/ ) );
10373 putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
10390 1/*upper lane*/ ) );
10407 putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/,
10424 0/*lower lane*/ ) );
10958 put it into the specified lane of xmm(G). */
10960 Int lane;
10967 lane = insn[3+1-1];
10968 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
10974 lane = insn[3+alen-1];
10976 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
10981 putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) );