Lines Matching refs:reg
47 void ppHRegAMD64 ( HReg reg )
54 if (hregIsVirtual(reg)) {
55 ppHReg(reg);
59 switch (hregClass(reg)) {
61 r = hregNumber(reg);
66 r = hregNumber(reg);
71 r = hregNumber(reg);
80 static void ppHRegAMD64_lo32 ( HReg reg )
87 if (hregIsVirtual(reg)) {
88 ppHReg(reg);
93 switch (hregClass(reg)) {
95 r = hregNumber(reg);
205 AMD64AMode* AMD64AMode_IR ( UInt imm32, HReg reg ) {
209 am->Aam.IR.reg = reg;
230 ppHRegAMD64(am->Aam.IR.reg);
248 addHRegUse(u, HRmRead, am->Aam.IR.reg);
262 am->Aam.IR.reg = lookupHRegRemap(m, am->Aam.IR.reg);
273 /* --------- Operand, which can be reg, immediate or memory. --------- */
281 AMD64RMI* AMD64RMI_Reg ( HReg reg ) {
284 op->Armi.Reg.reg = reg;
301 ppHRegAMD64_lo32(op->Armi.Reg.reg);
303 ppHRegAMD64(op->Armi.Reg.reg);
327 addHRegUse(u, HRmRead, op->Armi.Reg.reg);
342 op->Armi.Reg.reg = lookupHRegRemap(m, op->Armi.Reg.reg);
353 /* --------- Operand, which can be reg or immediate only. --------- */
361 AMD64RI* AMD64RI_Reg ( HReg reg ) {
364 op->Ari.Reg.reg = reg;
374 ppHRegAMD64(op->Ari.Reg.reg);
389 addHRegUse(u, HRmRead, op->Ari.Reg.reg);
401 op->Ari.Reg.reg = lookupHRegRemap(m, op->Ari.Reg.reg);
409 /* --------- Operand, which can be reg or memory only. --------- */
411 AMD64RM* AMD64RM_Reg ( HReg reg ) {
414 op->Arm.Reg.reg = reg;
430 ppHRegAMD64(op->Arm.Reg.reg);
448 /* reg is read, written or modified. Add it in the
450 addHRegUse(u, mode, op->Arm.Reg.reg);
464 op->Arm.Reg.reg = lookupHRegRemap(m, op->Arm.Reg.reg);
900 HReg reg, AMD64AMode* addr ) {
905 i->Ain.SseLdSt.reg = reg;
910 AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg reg, AMD64AMode* addr )
915 i->Ain.SseLdzLO.reg = reg;
983 //uu HReg reg, AMD64AMode* addr ) {
987 //uu i->Ain.AvxLdSt.reg = reg;
1240 ppHRegAMD64(i->Ain.SseLdSt.reg);
1242 ppHRegAMD64(i->Ain.SseLdSt.reg);
1251 ppHRegAMD64(i->Ain.SseLdzLO.reg);
1300 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1302 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1535 i->Ain.SseLdSt.reg);
1539 addHRegUse(u, HRmWrite, i->Ain.SseLdzLO.reg);
1581 /* reg-alloc needs to understand 'xor r,r' and 'cmpeqd
1604 //uu i->Ain.AvxLdSt.reg);
1759 mapReg(m, &i->Ain.SseLdSt.reg);
1763 mapReg(m, &i->Ain.SseLdzLO.reg);
1795 //uu mapReg(m, &i->Ain.AvxLdSt.reg);
1817 /* Figure out if i represents a reg-reg move, and if so assign the
1830 *src = i->Ain.Alu64R.src->Armi.Reg.reg;
1964 static UChar mkModRegRM ( UInt mod, UInt reg, UInt regmem )
1967 vassert((reg|regmem) < 8);
1969 | ((reg & 7) << 3)
2018 /* Forming mod-reg-rm bytes and scale-index-base bytes.
2051 && ! sameHReg(am->Aam.IR.reg, hregAMD64_RSP())
2052 && ! sameHReg(am->Aam.IR.reg, hregAMD64_RBP())
2053 && ! sameHReg(am->Aam.IR.reg, hregAMD64_R12())
2054 && ! sameHReg(am->Aam.IR.reg, hregAMD64_R13())
2057 iregBits210(am->Aam.IR.reg));
2061 && ! sameHReg(am->Aam.IR.reg, hregAMD64_RSP())
2062 && ! sameHReg(am->Aam.IR.reg, hregAMD64_R12())
2065 iregBits210(am->Aam.IR.reg));
2069 if (! sameHReg(am->Aam.IR.reg, hregAMD64_RSP())
2070 && ! sameHReg(am->Aam.IR.reg, hregAMD64_R12())
2073 iregBits210(am->Aam.IR.reg));
2077 if ((sameHReg(am->Aam.IR.reg, hregAMD64_RSP())
2078 || sameHReg(am->Aam.IR.reg, hregAMD64_R12()))
2085 if (/* (sameHReg(am->Aam.IR.reg, hregAMD64_RSP())
2087 sameHReg(am->Aam.IR.reg, hregAMD64_R12())) {
2122 /* Emit a mod-reg-rm byte when the rm bit denotes a reg. */
2145 UChar B = iregBit3(am->Aam.IR.reg);
2203 //uu vvvv=1111 (unused 3rd reg). */
2218 //uu rexB = iregBit3(am->Aam.IR.reg);
2276 UInt reg;
2295 /* Use the short form (load into 32 bit reg, + default
2337 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2340 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2359 i->Ain.Alu64R.src->Armi.Reg.reg);
2363 i->Ain.Alu64R.src->Armi.Reg.reg);
2432 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2435 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2455 *p++ = rexAMode_M(i->Ain.Alu64M.src->Ari.Reg.reg,
2458 p = doAMode_M(p, i->Ain.Alu64M.src->Ari.Reg.reg,
2496 /* testq sign-extend($imm32), %reg */
2566 rexAMode_R( i->Ain.Alu32R.src->Armi.Reg.reg,
2570 p = doAMode_R(p, i->Ain.Alu32R.src->Armi.Reg.reg,
2599 i->Ain.MulL.src->Arm.Reg.reg);
2602 i->Ain.MulL.src->Arm.Reg.reg);
2622 rexAMode_R( fake(0), i->Ain.Div.src->Arm.Reg.reg));
2625 i->Ain.Div.src->Arm.Reg.reg);
2642 i->Ain.Div.src->Arm.Reg.reg);
2645 i->Ain.Div.src->Arm.Reg.reg);
2666 *p++ = toUChar(0x40 + (1 & iregBit3(i->Ain.Push.src->Armi.Reg.reg)));
2667 *p++ = toUChar(0x50 + iregBits210(i->Ain.Push.src->Armi.Reg.reg));
2805 /* movq dstGA(a reg), amRIP -- copied from Alu64M MOV case */
2852 /* movq dstGA(a reg), amRIP -- copied from Alu64M MOV case */
2905 *p++ = rexAMode_R(i->Ain.CMov64.dst, i->Ain.CMov64.src->Arm.Reg.reg);
2908 p = doAMode_R(p, i->Ain.CMov64.dst, i->Ain.CMov64.src->Arm.Reg.reg);
2929 /* Produce a 32-bit reg-reg move, since the implicit
2975 reg = iregBits3210(i->Ain.Set64.dst);
2976 vassert(reg < 16);
2979 *p++ = toUChar(reg >= 8 ? 0x49 : 0x48);
2981 *p++ = toUChar(0xC0 + (reg & 7));
2986 *p++ = toUChar(reg >= 8 ? 0x41 : 0x40);
2989 *p++ = toUChar(0xC0 + (reg & 7));
3221 rexAMode_M( vreg2ireg(i->Ain.SseLdSt.reg), i->Ain.SseLdSt.addr));
3224 p = doAMode_M(p, vreg2ireg(i->Ain.SseLdSt.reg), i->Ain.SseLdSt.addr);
3232 rexAMode_M(vreg2ireg(i->Ain.SseLdzLO.reg),
3236 p = doAMode_M(p, vreg2ireg(i->Ain.SseLdzLO.reg),
3453 //uu UInt vex = vexAMode_M( dvreg2ireg(i->Ain.AvxLdSt.reg),
3457 //uu p = doAMode_M(p, dvreg2ireg(i->Ain.AvxLdSt.reg), i->Ain.AvxLdSt.addr);