Lines Matching refs:argR
1226 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1228 addInstr(env, AMD64Instr_MovxLQ(False, argR, argR));
1230 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) );
1425 IRExpr* argR = e->Iex.Unop.arg->Iex.Binop.arg2;
1440 AMD64RMI* rmi = iselIntExpr_RMI(env, argR);
2830 HReg argR = iselDblExpr(env, triop->arg3);
2834 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3364 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3367 addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst));
3380 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3383 addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
3399 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3402 addInstr(env, AMD64Instr_Sse32FLo(op, argR, dst));
3418 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3421 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3560 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3584 movupd %argR, 0(%rdx)
3588 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR,
3612 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
3637 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RDX()));
3667 HReg argR = iselVecExpr(env, triop->arg3);
3672 addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
3683 HReg argR = iselVecExpr(env, triop->arg3);
3688 addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst));