Cross Reference: /external/valgrind/main/VEX/priv/host_arm64

Lines Matching defs:nm
850 static void showARM64VecBinOp(/*OUT*/const HChar** nm,
853       case ARM64vecb_ADD64x2:   *nm = "add ";  *ar = "2d";  return;
854       case ARM64vecb_ADD32x4:   *nm = "add ";  *ar = "4s";  return;
855       case ARM64vecb_ADD16x8:   *nm = "add ";  *ar = "8h";  return;
856       case ARM64vecb_ADD8x16:   *nm = "add ";  *ar = "16b"; return;
857       case ARM64vecb_SUB64x2:   *nm = "sub ";  *ar = "2d";  return;
858       case ARM64vecb_SUB32x4:   *nm = "sub ";  *ar = "4s";  return;
859       case ARM64vecb_SUB16x8:   *nm = "sub ";  *ar = "8h";  return;
860       case ARM64vecb_SUB8x16:   *nm = "sub ";  *ar = "16b"; return;
861       case ARM64vecb_MUL32x4:   *nm = "mul ";  *ar = "4s";  return;
862       case ARM64vecb_MUL16x8:   *nm = "mul ";  *ar = "8h";  return;
863       case ARM64vecb_MUL8x16:   *nm = "mul ";  *ar = "16b"; return;
864       case ARM64vecb_FADD64x2:  *nm = "fadd";  *ar = "2d";  return;
865       case ARM64vecb_FSUB64x2:  *nm = "fsub";  *ar = "2d";  return;
866       case ARM64vecb_FMUL64x2:  *nm = "fmul";  *ar = "2d";  return;
867       case ARM64vecb_FDIV64x2:  *nm = "fdiv";  *ar = "2d";  return;
868       case ARM64vecb_FADD32x4:  *nm = "fadd";  *ar = "4s";  return;
869       case ARM64vecb_FSUB32x4:  *nm = "fsub";  *ar = "4s";  return;
870       case ARM64vecb_FMUL32x4:  *nm = "fmul";  *ar = "4s";  return;
871       case ARM64vecb_FDIV32x4:  *nm = "fdiv";  *ar = "4s";  return;
872       case ARM64vecb_UMAX32x4:  *nm = "umax";  *ar = "4s";  return;
873       case ARM64vecb_UMAX16x8:  *nm = "umax";  *ar = "8h";  return;
874       case ARM64vecb_UMAX8x16:  *nm = "umax";  *ar = "16b"; return;
875       case ARM64vecb_UMIN32x4:  *nm = "umin";  *ar = "4s";  return;
876       case ARM64vecb_UMIN16x8:  *nm = "umin";  *ar = "8h";  return;
877       case ARM64vecb_UMIN8x16:  *nm = "umin";  *ar = "16b"; return;
878       case ARM64vecb_UMULL32x2: *nm = "umull"; *ar = "2d"; return;
879       case ARM64vecb_UMULL16x4: *nm = "umull"; *ar = "4s"; return;
880       case ARM64vecb_UMULL8x8:  *nm = "umull"; *ar = "8b"; return;
881       case ARM64vecb_SMAX32x4:  *nm = "smax";  *ar = "4s";  return;
882       case ARM64vecb_SMAX16x8:  *nm = "smax";  *ar = "8h";  return;
883       case ARM64vecb_SMAX8x16:  *nm = "smax";  *ar = "16b"; return;
884       case ARM64vecb_SMIN32x4:  *nm = "smin";  *ar = "4s";  return;
885       case ARM64vecb_SMIN16x8:  *nm = "smin";  *ar = "8h";  return;
886       case ARM64vecb_SMIN8x16:  *nm = "smin";  *ar = "16b"; return;
887       case ARM64vecb_AND:       *nm = "and ";  *ar = "all"; return;
888       case ARM64vecb_ORR:       *nm = "orr ";  *ar = "all"; return;
889       case ARM64vecb_XOR:       *nm = "eor ";  *ar = "all"; return;
890       case ARM64vecb_CMEQ64x2:  *nm = "cmeq";  *ar = "2d";  return;
891       case ARM64vecb_CMEQ32x4:  *nm = "cmeq";  *ar = "4s";  return;
892       case ARM64vecb_CMEQ16x8:  *nm = "cmeq";  *ar = "8h";  return;
893       case ARM64vecb_CMEQ8x16:  *nm = "cmeq";  *ar = "16b"; return;
894       case ARM64vecb_CMHI64x2:  *nm = "cmhi";  *ar = "2d";  return;
895       case ARM64vecb_CMHI32x4:  *nm = "cmhi";  *ar = "4s";  return;
896       case ARM64vecb_CMHI16x8:  *nm = "cmhi";  *ar = "8h";  return;
897       case ARM64vecb_CMHI8x16:  *nm = "cmhi";  *ar = "16b"; return;
898       case ARM64vecb_CMGT64x2:  *nm = "cmgt";  *ar = "2d";  return;
899       case ARM64vecb_CMGT32x4:  *nm = "cmgt";  *ar = "4s";  return;
900       case ARM64vecb_CMGT16x8:  *nm = "cmgt";  *ar = "8h";  return;
901       case ARM64vecb_CMGT8x16:  *nm = "cmgt";  *ar = "16b"; return;
902       case ARM64vecb_FCMEQ64x2: *nm = "fcmeq"; *ar = "2d"; return;
903       case ARM64vecb_FCMEQ32x4: *nm = "fcmeq"; *ar = "4s"; return;
904       case ARM64vecb_FCMGE64x2: *nm = "fcmge"; *ar = "2d"; return;
905       case ARM64vecb_FCMGE32x4: *nm = "fcmge"; *ar = "4s"; return;
906       case ARM64vecb_FCMGT64x2: *nm = "fcmgt"; *ar = "2d"; return;
907       case ARM64vecb_FCMGT32x4: *nm = "fcmgt"; *ar = "4s"; return;
908       case ARM64vecb_TBL1:      *nm = "tbl ";  *ar = "16b"; return;
913 static void showARM64VecUnaryOp(/*OUT*/const HChar** nm,
917       case ARM64vecu_FNEG64x2:   *nm = "fneg   "; *ar = "2d";  return;
918       case ARM64vecu_FNEG32x4:   *nm = "fneg   "; *ar = "4s";  return;
919       case ARM64vecu_FABS64x2:   *nm = "fabs   "; *ar = "2d";  return;
920       case ARM64vecu_FABS32x4:   *nm = "fabs   "; *ar = "4s";  return;
921       case ARM64vecu_VMOVL8U:    *nm = "vmovl.u8"; *ar = "all"; return;
922       case ARM64vecu_VMOVL16U:   *nm = "vmovl.u16"; *ar = "all"; return;
923       case ARM64vecu_VMOVL32U:   *nm = "vmovl.u32"; *ar = "all"; return;
924       case ARM64vecu_VMOVL8S:    *nm = "vmovl.s8"; *ar = "all"; return;
925       case ARM64vecu_VMOVL16S:   *nm = "vmovl.s16"; *ar = "all"; return;
926       case ARM64vecu_VMOVL32S:   *nm = "vmovl.s32"; *ar = "all"; return;
927       case ARM64vecu_NOT:        *nm = "not    "; *ar = "all"; return;
928       case ARM64vecu_CNT:        *nm = "cnt    "; *ar = "16b"; return;
929       case ARM64vecu_UADDLV8x16: *nm = "uaddlv "; *ar = "16b"; return;
930       case ARM64vecu_UADDLV16x8: *nm = "uaddlv "; *ar = "8h"; return;
931       case ARM64vecu_UADDLV32x4: *nm = "uaddlv "; *ar = "4s"; return;
932       case ARM64vecu_SADDLV8x16: *nm = "saddlv "; *ar = "16b"; return;
933       case ARM64vecu_SADDLV16x8: *nm = "saddlv "; *ar = "8h"; return;
934       case ARM64vecu_SADDLV32x4: *nm = "saddlv "; *ar = "4s"; return;
939 static void showARM64VecShiftOp(/*OUT*/const HChar** nm,
944       case ARM64vecsh_USHR64x2: *nm = "ushr  "; *ar = "2d";  return;
945       case ARM64vecsh_USHR32x4: *nm = "ushr  "; *ar = "4s";  return;
946       case ARM64vecsh_USHR16x8: *nm = "ushr  "; *ar = "8h";  return;
947       case ARM64vecsh_USHR8x16: *nm = "ushr  "; *ar = "16b"; return;
948       case ARM64vecsh_SSHR64x2: *nm = "sshr  "; *ar = "2d";  return;
949       case ARM64vecsh_SSHR32x4: *nm = "sshr  "; *ar = "4s";  return;
950       case ARM64vecsh_SSHR16x8: *nm = "sshr  "; *ar = "8h";  return;
951       case ARM64vecsh_SSHR8x16: *nm = "sshr  "; *ar = "16b"; return;
952       case ARM64vecsh_SHL64x2:  *nm = "shl   "; *ar = "2d";  return;
953       case ARM64vecsh_SHL32x4:  *nm = "shl   "; *ar = "4s";  return;
954       case ARM64vecsh_SHL16x8:  *nm = "shl   "; *ar = "8h";  return;
955       case ARM64vecsh_SHL8x16:  *nm = "shl   "; *ar = "16b"; return;
2276          const HChar* nm = "??";
2278          showARM64VecBinOp(&nm, &ar, i->ARM64in.VBinV.op);
2279          vex_printf("%s   ", nm);
2289          const HChar* nm = "??";
2291          showARM64VecUnaryOp(&nm, &ar, i->ARM64in.VUnaryV.op);
2292          vex_printf("%s  ", nm);
2311          const HChar* nm = "??";
2313          showARM64VecShiftOp(&nm, &ar, i->ARM64in.VShiftImmV.op);
2314          vex_printf("%s ", nm);
2370 //ZZ          const HChar* nm = "?";
2372 //ZZ             nm = i->ARMin.VCvtID.syned ? "fsitod" : "fuitod";
2374 //ZZ             nm = i->ARMin.VCvtID.syned ? "ftosid" : "ftouid";
2376 //ZZ          vex_printf("%s ", nm);