Lines Matching refs:mode64
53 static Bool mode64 = False;
121 Bool mode64;
152 vassert(env->mode64);
164 ppMIPSInstr(instr, mode64);
171 HReg reg = mkHReg(env->vreg_ctr, HRcGPR(env->mode64),
194 HReg sp = StackPointer(mode64);
196 if (mode64)
206 HReg sp = StackPointer(mode64);
208 if (mode64)
296 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
299 addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
310 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
312 addInstr(env, MIPSInstr_Load(4, fcsr, am_addr, mode64));
363 am_addr0 = MIPSAMode_IR(0, StackPointer(mode64));
364 am_addr1 = MIPSAMode_IR(4, StackPointer(mode64));
368 addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcLo, mode64));
369 addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcHi, mode64));
371 addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcHi, mode64));
372 addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcLo, mode64));
454 if (mode64) {
455 argregs[0] = hregMIPS_GPR4(mode64);
456 argregs[1] = hregMIPS_GPR5(mode64);
457 argregs[2] = hregMIPS_GPR6(mode64);
458 argregs[3] = hregMIPS_GPR7(mode64);
459 argregs[4] = hregMIPS_GPR8(mode64);
460 argregs[5] = hregMIPS_GPR9(mode64);
461 argregs[6] = hregMIPS_GPR10(mode64);
462 argregs[7] = hregMIPS_GPR11(mode64);
468 argregs[0] = hregMIPS_GPR4(mode64);
469 argregs[1] = hregMIPS_GPR5(mode64);
470 argregs[2] = hregMIPS_GPR6(mode64);
471 argregs[3] = hregMIPS_GPR7(mode64);
520 if (aTy == Ity_I32 || mode64) {
540 GuestStatePointer(mode64)));
561 if (aTy == Ity_I32 || (mode64 && arg->tag != Iex_BBPTR)) {
576 tmpregs[argreg] = GuestStatePointer(mode64);
622 *retloc = mk_RetLoc_simple(mode64 ? RLPri_Int : RLPri_2Int);
643 ULong target = mode64 ? Ptr_to_ULong(cee->addr) :
691 return toBool(hregClass(am->Mam.IR.base) == HRcGPR(mode64) &&
695 return toBool(hregClass(am->Mam.RR.base) == HRcGPR(mode64) &&
697 hregClass(am->Mam.RR.index) == HRcGPR(mode64) &&
716 if (env->mode64) {
777 All results are returned in a (mode64 ? 64bit : 32bit) register.
787 vassert(hregClass(r) == HRcGPR(env->mode64));
798 || ty == Ity_F32 || (ty == Ity_I64 && mode64)
799 || (ty == Ity_I128 && mode64));
816 r_dst, am_addr, mode64));
925 if (mode64)
933 if (mode64 && (shftOp == Mshft_SRA || shftOp == Mshft_SRL)) {
954 vassert(mode64);
1110 if (mode64) {
1257 vassert(mode64);
1278 vassert(mode64);
1297 if (mode64)
1338 rloc = mode64 ? mk_RetLoc_simple(RLPri_Int) :
1349 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR4(env->mode64), regL));
1350 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR5(env->mode64), regR));
1356 addInstr(env, mk_iMOVds_RR(res, hregMIPS_GPR2(env->mode64)));
1463 vassert(mode64);
1476 if (mode64)
1510 vassert(mode64);
1541 vassert(mode64);
1547 vassert(mode64);
1553 vassert(mode64);
1569 vassert(mode64);
1578 if (env->mode64) {
1592 if (env->mode64) {
1604 vassert(env->mode64);
1613 vassert(mode64);
1629 hregMIPS_GPR0(mode64), MIPScc_NE));
1638 hregMIPS_GPR0(mode64), MIPScc_NE));
1646 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
1660 if (op_unop == Iop_Left64 && !mode64)
1666 hregMIPS_GPR0(mode64),
1674 vassert(mode64);
1687 if (env->mode64) {
1694 addInstr(env, MIPSInstr_Cmp(False, !(env->mode64), r_dst, r_src,
1695 hregMIPS_GPR0(mode64), MIPScc_NE));
1702 vassert(env->mode64);
1705 addInstr(env, MIPSInstr_Alu(Malu_DSUB, tmp2, hregMIPS_GPR0(mode64),
1715 vassert(mode64);
1722 vassert(mode64);
1749 rloc = mode64 ? mk_RetLoc_simple(RLPri_Int) :
1759 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR4(env->mode64), regL));
1764 addInstr(env, mk_iMOVds_RR(res, hregMIPS_GPR2(env->mode64)));
1774 || ((ty == Ity_I64) && mode64)) {
1778 GuestStatePointer(mode64));
1780 mode64));
1812 if (!mode64)
1852 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
1890 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
1905 ((ty == Ity_I64) && env->mode64));
1914 vassert(env->mode64);
1999 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
2115 MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
2118 MIPSAMode_IR(am_addr->Mam.IR.index + COND_OFFSET(mode64),
2120 dst, mode64));
2131 MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
2134 MIPSAMode_IR(am_addr->Mam.IR.index + COND_OFFSET(mode64),
2136 r_dst, mode64));
2142 MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
2145 MIPSAMode_IR(am_addr->Mam.IR.index + COND_OFFSET(mode64),
2147 r_dst, mode64));
2168 vassert(env->mode64);
2170 vassert(hregClass(*rHi) == HRcGPR(env->mode64));
2172 vassert(hregClass(*rLo) == HRcGPR(env->mode64));
2233 vassert(mode64);
2269 vassert(!env->mode64);
2293 addInstr(env, MIPSInstr_Load(4, tHi, MIPSAMode_IR(0, r_addr), mode64));
2294 addInstr(env, MIPSInstr_Load(4, tLo, MIPSAMode_IR(4, r_addr), mode64));
2330 GuestStatePointer(mode64));
2331 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2332 addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeInt(am_addr), mode64));
2768 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
2775 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2777 mode64));
2779 addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64));
2781 mode64));
2841 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2842 MIPSRH_Reg(hregMIPS_GPR0(mode64))));
2854 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2855 MIPSRH_Reg(hregMIPS_GPR0(mode64))));
2903 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
2921 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
2928 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2930 mode64));
2932 addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64));
2934 mode64));
2998 GuestStatePointer(mode64));
3032 if (mode64) {
3078 vassert(mode64);
3085 vassert(mode64);
3092 vassert(mode64);
3099 vassert(mode64);
3171 if (mode64)
3223 if (mode64) {
3228 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
3231 addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
3256 if (mode64) {
3261 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
3264 addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
3372 MIPSAMode *zero_r1 = MIPSAMode_IR(0, StackPointer(mode64));
3387 vassert(mode64);
3438 GuestStatePointer(mode64));
3453 vassert(!mode64);
3470 vassert(!mode64);
3647 (mode64 && (tyd == Ity_I64))) {
3650 am_addr, r_src, mode64));
3653 if (!mode64 && (tyd == Ity_I64)) {
3660 MIPSAMode_IR(0, r_addr), vHi, mode64));
3662 MIPSAMode_IR(4, r_addr), vLo, mode64));
3671 if (tyd == Ity_F64 && mode64) {
3677 if (!mode64 && (tyd == Ity_F64)) {
3692 (ty == Ity_I64 && mode64)) {
3695 GuestStatePointer(mode64));
3697 am_addr, r_src, mode64));
3701 if (ty == Ity_I64 && !mode64) {
3704 GuestStatePointer(mode64));
3706 GuestStatePointer(mode64));
3709 am_addr, vLo, mode64));
3711 am_addr4, vHi, mode64));
3719 GuestStatePointer(mode64));
3728 GuestStatePointer(mode64));
3749 if (mode64) {
3764 if (mode64 && ty == Ity_I128) {
3781 if (mode64) {
3840 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
3846 if (mode64) {
3850 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
3858 addInstr(env, mk_iMOVds_RR(rLo, hregMIPS_GPR2(mode64)));
3859 addInstr(env, mk_iMOVds_RR(rHi, hregMIPS_GPR3(mode64)));
3875 MIPSAMode* am = MIPSAMode_IR(rloc.spOff, StackPointer(mode64));
3876 addInstr(env, MIPSInstr_Load(mode64 ? 8 : 4, dst, am, mode64));
3897 if (!mode64 && (tyAddr != Ity_I32))
3908 addInstr(env, MIPSInstr_LoadL(4, r_dst, r_addr, mode64));
3910 } else if (tyRes == Ity_I64 && mode64) {
3911 addInstr(env, MIPSInstr_LoadL(8, r_dst, r_addr, mode64));
3925 addInstr(env, MIPSInstr_StoreC(4, r_addr, r_dst, mode64));
3927 } else if (tyData == Ity_I64 && mode64) {
3929 addInstr(env, MIPSInstr_StoreC(8, r_addr, r_dst, mode64));
3955 if (!mode64 && dst->tag != Ico_U32)
3957 if (mode64 && dst->tag != Ico_U64)
3962 GuestStatePointer(mode64));
3973 = mode64
3978 mode64 ? (Addr64)stmt->Ist.Exit.dst->Ico.U64
4047 vassert(cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32));
4050 MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
4056 = env->mode64
4061 env->mode64 ? (Addr64)cdst->Ico.U64
4081 GuestStatePointer(env->mode64));
4110 MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
4153 mode64 = arch_host != VexArchMIPS32;
4162 env->mode64 = mode64;
4193 if (mode64) {
4201 if (mode64) {
4210 vassert(mode64);
4215 if (mode64) {
4236 amCounter = MIPSAMode_IR(offs_Host_EvC_Counter, GuestStatePointer(mode64));
4237 amFailAddr = MIPSAMode_IR(offs_Host_EvC_FailAddr, GuestStatePointer(mode64));