Cross Reference: /external/valgrind/main/callgrind/sim.c

Lines Matching defs:simulator
101 /* Cache simulator Options */
148 } simulator;
1068     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
1093     Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);
1095     Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);
1126     Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);
1128     Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);
1130     Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size);
1165     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
1166     DrRes = (*simulator.D1_Read)(data_addr, data_size);
1201     DrRes = (*simulator.D1_Read)(data_addr, data_size);
1228     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);
1229     DwRes = (*simulator.D1_Write)(data_addr, data_size);
1261     DwRes = (*simulator.D1_Write)(data_addr, data_size);
1289 /* Initialize and clear simulator state */
1327   // accesses to the simulator straddling more than two
1353    * with dispatching via simulator struct */
1389       simulator.I1_Read  = cacheuse_I1_doRead;
1390       simulator.D1_Read  = cacheuse_D1_doRead;
1391       simulator.D1_Write = cacheuse_D1_doRead;
1399       simulator.I1_Read  = prefetch_I1_Read;
1400       simulator.D1_Read  = prefetch_D1_Read;
1401       simulator.D1_Write = prefetch_D1_Write;
1404       simulator.I1_Read  = prefetch_I1_ref;
1405       simulator.D1_Read  = prefetch_D1_ref;
1406       simulator.D1_Write = prefetch_D1_ref;
1413       simulator.I1_Read  = cachesim_I1_Read;
1414       simulator.D1_Read  = cachesim_D1_Read;
1415       simulator.D1_Write = cachesim_D1_Write;
1418       simulator.I1_Read  = cachesim_I1_ref;
1419       simulator.D1_Read  = cachesim_D1_ref;
1420       simulator.D1_Write = cachesim_D1_ref;
1425 /* Clear simulator state. Has to be initialized before */
1449 "\n   cache simulator options (does cache simulation if used):\n"
1776 /*--- The simulator defined in this file                   ---*/