Cross Reference: /external/valgrind/main/coregrind/m

Lines Matching defs:ci
50 add_cache(VexCacheInfo *ci, VexCache cache)
54    if (ci->num_caches == num_allocated) {
56       ci->caches = VG_(realloc)("m_cache", ci->caches,
57                                 num_allocated * sizeof *ci->caches);
60    if (ci->num_levels < cache.level) ci->num_levels = cache.level;
61    ci->caches[ci->num_caches++] = cache;
67       add_cache(ci, \
73       add_cache(ci, \
79       add_cache(ci, \
88       add_cache(ci, c); \
113 Intel_cache_info(Int level, VexCacheInfo *ci)
145    ci->num_levels = 0;
146    ci->num_caches = 0;
147    ci->icaches_maintain_coherence = True;
148    ci->caches = NULL;
411 AMD_cache_info(VexCacheInfo *ci)
438    ci->num_levels = 2;
439    ci->num_caches = 3;
440    ci->icaches_maintain_coherence = True;
444       ci->num_levels = 3;
445       ci->num_caches = 4;
448    ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);
454    ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE, 1, size, line_size, assoc);
460    ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE, 1, size, line_size, assoc);
466    ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, size, line_size, assoc);
477       ci->caches[3] = VEX_CACHE_INIT(UNIFIED_CACHE, 3, size, line_size, assoc);
484 get_caches_from_CPUID(VexCacheInfo *ci)
502       ret = Intel_cache_info(level, ci);
505       ret = AMD_cache_info(ci);
509       ci->num_levels = 2;
510       ci->num_caches = 3;
511       ci->icaches_maintain_coherence = True;
512       ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);
513       ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE,    1, 64, 16, 16);
514       ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE,    1, 64, 16,  4);
515       ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, 64, 16, 16);
526    for (i = 0; i < ci->num_caches; ++i) {
527       ci->caches[i].sizeB *= 1024;
605    VexCacheInfo *ci = &vai->hwcache_info;
607    ci->icaches_maintain_coherence = True;
619    ci->num_levels = 0;
620    ci->num_caches = 0;
625       ++ci->num_levels;
629       case 0:  ci->num_caches += 2; break; /* separate data and insn cache */
630       case 1:  ci->num_caches += 1; break; /* only insn cache */
631       case 2:  ci->num_caches += 1; break; /* only data cache */
632       case 3:  ci->num_caches += 1; break; /* unified data and insn cache */
636    ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);
639    for (level = 0; level < ci->num_levels; level++) {
644          ci->caches[i++] = get_cache(level, INSN_CACHE);
645          ci->caches[i++] = get_cache(level, DATA_CACHE);
649          ci->caches[i++] = get_cache(level, INSN_CACHE);
653          ci->caches[i++] = get_cache(level, DATA_CACHE);
657          ci->caches[i++] = get_cache(level, UNIFIED_CACHE);
672 write_cache_info(const VexCacheInfo *ci)
677    VG_(debugLog)(1, "cache", "  #levels = %u\n", ci->num_levels);
678    VG_(debugLog)(1, "cache", "  #caches = %u\n", ci->num_caches);
679    for (i = 0; i < ci->num_caches; ++i) {
680       VexCache *c = ci->caches + i;
698 cache_info_is_sensible(const VexCacheInfo *ci)
706    for (level = 1; level <= ci->num_levels; ++level) {
710       for (i = 0; i < ci->num_caches; ++i) {
711          if (ci->caches[i].level == level) {
712             switch (ci->caches[i].kind) {
736    for (level = 2; level <= ci->num_levels; ++level) {
738       for (i = 0; i < ci->num_caches; ++i) {
739          if (ci->caches[i].level == level - 1) {
762    VexCacheInfo *ci = &vai->hwcache_info;
767       ok = cache_info_is_sensible(ci);
776       write_cache_info(ci);  /* write out for debugging */
781       ci->num_levels = 0;
782       ci->num_caches = 0;
783       VG_(free)(ci->caches);
784       ci->caches = NULL;