Lines Matching defs:shift
214 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
216 shift_(shift),
294 Shift shift,
297 shift_(shift), extend_(NO_EXTEND), shift_amount_(shift_amount) {
300 VIXL_ASSERT(shift == LSL);
314 shift_= offset.shift();
1548 int shift,
1550 if (shift >= 0) {
1551 // Explicit shift specified.
1552 VIXL_ASSERT((shift == 0) || (shift == 16) ||
1553 (shift == 32) || (shift == 48));
1554 VIXL_ASSERT(rd.Is64Bits() || (shift == 0) || (shift == 16));
1555 shift /= 16;
1557 // Calculate a new immediate and shift combination to encode the immediate
1559 shift = 0;
1564 shift = 1;
1568 shift = 2;
1572 shift = 3;
1579 Rd(rd) | ImmMoveWide(imm) | ShiftMoveWide(shift));
1597 VIXL_ASSERT(operand.shift() != ROR);
1749 Shift shift,
1751 switch (shift) {
1780 // Number of bits left in the result that are not introduced by the shift.
1794 // Nothing to extend. Just shift.
1816 ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
1859 Shift shift = addr.shift();
1863 if (shift == LSL) {
1867 // Shifts are encoded in one bit, indicating a left shift by the memory