Lines Matching defs:Rm
376 uint32_t Rm;
382 Rm = mAddrMode.reg_imm_Rm;
388 Rm = Op2;
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
472 int Rm = mAddrMode.reg_imm_Rm;
474 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount);
478 int Rm = Op2;
480 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount);
488 int Rm = mTmpReg1;
490 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount);
519 void ArmToArm64Assembler::MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn)
523 *mPC++ = A64_MADD_W(Rd, Rm, Rs, Rn);
527 void ArmToArm64Assembler::MUL(int cc, int s, int Rd, int Rm, int Rs)
531 *mPC++ = A64_MADD_W(Rd, Rm, Rs, mZeroReg);
534 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
539 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
544 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
549 int /*RdLo*/, int /*RdHi*/, int /*Rm*/, int /*Rs*/)
726 void ArmToArm64Assembler::SWP(int /*cc*/, int /*Rn*/, int /*Rd*/, int /*Rm*/)
730 void ArmToArm64Assembler::SWPB(int /*cc*/, int /*Rn*/, int /*Rd*/, int /*Rm*/)
746 void ArmToArm64Assembler::CLZ(int /*cc*/, int /*Rd*/, int /*Rm*/)
751 void ArmToArm64Assembler::QADD(int /*cc*/, int /*Rd*/, int /*Rm*/, int /*Rn*/)
756 void ArmToArm64Assembler::QDADD(int /*cc*/, int /*Rd*/, int /*Rm*/, int /*Rn*/)
761 void ArmToArm64Assembler::QSUB(int /*cc*/, int /*Rd*/, int /*Rm*/, int /*Rn*/)
766 void ArmToArm64Assembler::QDSUB(int /*cc*/, int /*Rd*/, int /*Rm*/, int /*Rn*/)
775 int Rd, int Rm, int Rs)
780 *mPC++ = A64_SBFM_W(mTmpReg1, Rm, 16, 31);
782 *mPC++ = A64_SBFM_W(mTmpReg1, Rm, 0, 15);
794 void ArmToArm64Assembler::SMULW(int cc, int y, int Rd, int Rm, int Rs)
803 *mPC++ = A64_SBFM_W(mTmpReg2, Rm, 0, 31);
810 void ArmToArm64Assembler::SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn)
815 *mPC++ = A64_SBFM_W(mTmpReg1, Rm, 0, 15);
821 int /*RdHi*/, int /*RdLo*/, int /*Rs*/, int /*Rm*/)
828 int /*Rd*/, int /*Rm*/, int /*Rs*/, int /*Rn*/)
837 void ArmToArm64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
841 *mPC++ = A64_EXTR_W(mTmpReg1, Rm, Rm, rotate * 8);
885 uint32_t ArmToArm64Assembler::reg_imm(int Rm, int type, uint32_t shift)
887 mAddrMode.reg_imm_Rm = Rm;
893 uint32_t ArmToArm64Assembler::reg_rrx(int /*Rm*/)
899 uint32_t ArmToArm64Assembler::reg_reg(int /*Rm*/, int /*type*/, int /*Rs*/)
925 uint32_t ArmToArm64Assembler::reg_scale_pre(int Rm, int type,
935 mAddrMode.reg_offset = Rm;
940 uint32_t ArmToArm64Assembler::reg_scale_post(int /*Rm*/, int /*type*/, uint32_t /*shift*/)
964 uint32_t ArmToArm64Assembler::reg_pre(int Rm, int W)
973 mAddrMode.reg_offset = Rm;
978 uint32_t ArmToArm64Assembler::reg_post(int /*Rm*/)
1004 uint32_t Rn, uint32_t Rm)
1009 dataTransferOpName[op], Rt, Rn, Rm);
1010 return(dataTransferOpCode[op] | (Rm << 16) | (Rn << 5) | Rt);
1015 dataTransferOpName[op], Rt, Rn, Rm);
1016 return(dataTransferOpCode[op] | (0x1<<30) | (Rm<<16) | (Rn<<5)|Rt);
1047 uint32_t Rm,
1050 LOG_INSTR("ADD X%d, X%d, W%d, SXTW #%d\n", Rd, Rn, Rm, amount);
1051 return ((0x8B << 24) | (0x1 << 21) |(Rm << 16) |
1058 uint32_t Rm,
1061 LOG_INSTR("SUB X%d, X%d, W%d, SXTW #%d\n", Rd, Rn, Rm, amount);
1062 return ((0xCB << 24) | (0x1 << 21) |(Rm << 16) |
1074 uint32_t Rm, uint32_t shift,
1078 Rd, Rn, Rm, shift_codes[shift], amount);
1079 return ((0x8B << 24) | (shift << 22) | ( Rm << 16) |
1097 uint32_t Rm, uint32_t shift,
1101 Rd, Rn, Rm, shift_codes[shift], amount);
1102 return ((0x0B << 24) | (shift << 22) | ( Rm << 16) |
1107 uint32_t Rm, uint32_t shift,
1114 Rd, Rn, Rm, shift_codes[shift], amount);
1115 return ((0x4B << 24) | (shift << 22) | ( Rm << 16) |
1121 Rd, Rn, Rm, shift_codes[shift], amount);
1122 return ((0x6B << 24) | (shift << 22) | ( Rm << 16) |
1128 uint32_t Rm, uint32_t shift,
1132 Rd, Rn, Rm, shift_codes[shift], amount);
1133 return ((0x0A << 24) | (shift << 22) | ( Rm << 16) |
1138 uint32_t Rm, uint32_t shift,
1142 Rd, Rn, Rm, shift_codes[shift], amount);
1143 return ((0x2A << 24) | (shift << 22) | ( Rm << 16) |
1148 uint32_t Rm, uint32_t shift,
1152 Rd, Rn, Rm, shift_codes[shift], amount);
1153 return ((0x2A << 24) | (shift << 22) | (0x1 << 21) | ( Rm << 16) |
1158 uint32_t Rm, uint32_t cond)
1160 LOG_INSTR("CSEL X%d, X%d, X%d, %s\n", Rd, Rn, Rm, cc_codes[cond]);
1161 return ((0x9A << 24)|(0x1 << 23)|(Rm << 16) |(cond << 12)| (Rn << 5) | Rd);
1165 uint32_t Rm, uint32_t cond)
1167 LOG_INSTR("CSEL W%d, W%d, W%d, %s\n", Rd, Rn, Rm, cc_codes[cond]);
1168 return ((0x1A << 24)|(0x1 << 23)|(Rm << 16) |(cond << 12)| (Rn << 5) | Rd);
1199 uint32_t Rm, uint32_t Ra)
1201 LOG_INSTR("SMADDL X%d, W%d, W%d, X%d\n",Rd, Rn, Rm, Ra);
1202 return ((0x9B << 24) | (0x1 << 21) | (Rm << 16)|(Ra << 10)|(Rn << 5) | Rd);
1206 uint32_t Rm, uint32_t Ra)
1208 LOG_INSTR("MADD W%d, W%d, W%d, W%d\n",Rd, Rn, Rm, Ra);
1209 return ((0x1B << 24) | (Rm << 16) | (Ra << 10) |(Rn << 5) | Rd);
1235 uint32_t Rm, uint32_t lsb)
1237 LOG_INSTR("EXTR W%d, W%d, W%d, #%d\n", Rd, Rn, Rm, lsb);
1238 return (0x13 << 24)|(0x1 << 23) | (Rm << 16) | (lsb << 10)|(Rn << 5) | Rd;