/external/llvm/lib/Analysis/ |
H A D | CGSCCPassManager.cpp | 21 CGSCCAnalysisManager *AM) { 31 PreservedAnalyses PassPA = Passes[Idx]->run(C, AM); 32 if (AM) 33 AM->invalidate(C, PassPA); 20 run(LazyCallGraph::SCC *C, CGSCCAnalysisManager *AM) argument
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H A D | TypeBasedAliasAnalysis.cpp | 457 const MDNode *AM = LocA.TBAATag; local 458 if (!AM) return AliasAnalysis::alias(LocA, LocB); 463 if (Aliases(AM, BM))
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H A D | LazyCallGraph.cpp | 712 ModuleAnalysisManager *AM) { 713 LazyCallGraph &G = AM->getResult<LazyCallGraphAnalysis>(M); 711 run(Module *M, ModuleAnalysisManager *AM) argument
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H A D | DependenceAnalysis.cpp | 1277 // Computes the GCD of AM and BM. 1281 bool findGCD(unsigned Bits, APInt AM, APInt BM, APInt Delta, argument 1285 APInt G0 = AM.abs(); 1298 X = AM.slt(0) ? -A1 : A1; 1378 DEBUG(dbgs() << "\t SrcCoeff = " << *SrcCoeff << " = AM\n"); 1398 APInt AM = ConstSrcCoeff->getValue()->getValue(); local 1400 unsigned Bits = AM.getBitWidth(); 1401 if (findGCD(Bits, AM, BM, ConstDelta->getValue()->getValue(), G, X, Y)) { 1443 // test(AM/G, LM-Y) and test(-AM/ 1802 APInt AM = ConstSrcCoeff->getValue()->getValue(); local [all...] |
/external/llvm/lib/IR/ |
H A D | PassManager.cpp | 22 PreservedAnalyses ModulePassManager::run(Module *M, ModuleAnalysisManager *AM) { argument 32 PreservedAnalyses PassPA = Passes[Idx]->run(M, AM); 33 if (AM) 34 AM->invalidate(M, PassPA); 84 FunctionAnalysisManager *AM) { 94 PreservedAnalyses PassPA = Passes[Idx]->run(F, AM); 95 if (AM) 96 AM->invalidate(F, PassPA); 83 run(Function *F, FunctionAnalysisManager *AM) argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 329 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { argument 330 switch (AM) { 468 const char *AM = getIndexedModeName(LD->getAddressingMode()); local 469 if (*AM) 470 OS << ", " << AM; local 479 const char *AM = getIndexedModeName(ST->getAddressingMode()); local 480 if (*AM) 481 OS << ", " << AM; local
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/external/libphonenumber/java/test/com/android/i18n/phonenumbers/ |
H A D | RegionCode.java | 27 static final String AM = "AM"; field in class:RegionCode
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/external/llvm/include/llvm/Analysis/ |
H A D | CGSCCPassManager.h | 44 CGSCCAnalysisManager *AM = nullptr); 326 PreservedAnalyses run(Module *M, ModuleAnalysisManager *AM) { argument 327 assert(AM && "We need analyses to compute the call graph!"); 331 AM->getResult<CGSCCAnalysisManagerModuleProxy>(M).getManager(); 334 LazyCallGraph &CG = AM->getResult<LazyCallGraphAnalysis>(M); 544 PreservedAnalyses run(LazyCallGraph::SCC *C, CGSCCAnalysisManager *AM) { argument 546 if (AM) 548 FAM = &AM->getResult<FunctionAnalysisManagerCGSCCProxy>(C).getManager();
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 108 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); 109 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); 110 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); 140 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { argument 143 if (AM.hasSymbolicDisplacement()) 149 AM.GV = G->getGlobal(); 150 AM.Disp += G->getOffset(); 151 //AM.SymbolFlags = G->getTargetFlags(); 153 AM.CP = CP->getConstVal(); 154 AM 172 MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) argument 185 MatchAddress(SDValue N, MSP430ISelAddressMode &AM) argument 251 MSP430ISelAddressMode AM; local 305 ISD::MemIndexedMode AM = LD->getAddressingMode(); local [all...] |
H A D | MSP430ISelLowering.cpp | 1115 ISD::MemIndexedMode &AM, 1137 AM = ISD::POST_INC; 1112 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 124 const X86AddressMode &AM) { 125 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8); 127 if (AM.BaseType == X86AddressMode::RegBase) 128 MIB.addReg(AM.Base.Reg); 130 assert(AM.BaseType == X86AddressMode::FrameIndexBase); 131 MIB.addFrameIndex(AM.Base.FrameIndex); 134 MIB.addImm(AM 123 addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) argument [all...] |
/external/llvm/unittests/IR/ |
H A D | PassManagerTest.cpp | 35 Result run(Function *F, FunctionAnalysisManager *AM) { argument 65 Result run(Module *M, ModuleAnalysisManager *AM) { argument 101 PreservedAnalyses run(Module *M, ModuleAnalysisManager *AM) { argument 105 (void)AM->getResult<TestModuleAnalysis>(M); 122 PreservedAnalyses run(Function *F, FunctionAnalysisManager *AM) { argument 126 AM->getResult<ModuleAnalysisManagerFunctionProxy>(F).getManager(); 134 AM->getCachedResult<TestFunctionAnalysis>(F)) 138 TestFunctionAnalysis::Result &AR = AM->getResult<TestFunctionAnalysis>(F);
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/external/llvm/lib/CodeGen/ |
H A D | BasicTargetTransformInfo.cpp | 151 TargetLoweringBase::AddrMode AM; local 152 AM.BaseGV = BaseGV; 153 AM.BaseOffs = BaseOffset; 154 AM.HasBaseReg = HasBaseReg; 155 AM.Scale = Scale; 156 return getTLI()->isLegalAddressingMode(AM, Ty); 162 TargetLoweringBase::AddrMode AM; local 163 AM.BaseGV = BaseGV; 164 AM.BaseOffs = BaseOffset; 165 AM [all...] |
H A D | TargetLoweringBase.cpp | 1427 /// by AM is legal for this target, for a load/store of the specified type. 1428 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, argument 1434 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1438 if (AM.BaseGV) 1442 switch (AM.Scale) { 1446 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1451 if (AM.HasBaseReg || AM [all...] |
H A D | CodeGenPrepare.cpp | 1054 static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) { argument 1055 AM.print(OS); 1527 Instruction *MI, ExtAddrMode &AM, 1531 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM), 1525 AddressingModeMatcher(SmallVectorImpl<Instruction*> &AMI, const TargetLowering &T, Type *AT, Instruction *MI, ExtAddrMode &AM, const SetOfInstrs &InsertedTruncs, InstrToOrigTy &PromotedInsts, TypePromotionTransaction &TPT) argument
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/external/llvm/include/llvm/IR/ |
H A D | PassManager.h | 173 virtual PreservedAnalyses run(IRUnitT IR, AnalysisManagerT *AM) = 0; 228 PreservedAnalyses run(IRUnitT IR, AnalysisManagerT *AM) override { 229 return Pass.run(IR, AM); 254 PreservedAnalyses run(IRUnitT IR, AnalysisManagerT *AM) override { 382 run(IRUnitT IR, AnalysisManagerT *AM) = 0; 422 run(IRUnitT IR, AnalysisManagerT *AM) override { 423 return make_unique<ResultModelT>(Pass.run(IR, AM)); 483 PreservedAnalyses run(Module *M, ModuleAnalysisManager *AM = nullptr); 527 PreservedAnalyses run(Function *F, FunctionAnalysisManager *AM = nullptr); 989 PreservedAnalyses run(Module *M, ModuleAnalysisManager *AM) { argument [all...] |
/external/chromium_org/third_party/icu/source/i18n/unicode/ |
H A D | calendar.h | 132 * saving time in US, wall clock time jumps from 1:00 AM (standard) to 2:00 AM 133 * (daylight). Therefore, wall clock time from 1:00 AM to 1:59 AM do not exist on 136 * In this example, 1:30 AM is interpreted as 1:30 AM standard time (non-exist), 137 * so the final result will be 2:30 AM daylight time. 140 * hour at 2:00 AM. So wall clock time from 1:00 AM to 1:59 AM occu 288 AM, enumerator in enum:Calendar::EAmpm [all...] |
/external/icu/icu4c/source/i18n/unicode/ |
H A D | calendar.h | 132 * saving time in US, wall clock time jumps from 1:00 AM (standard) to 2:00 AM 133 * (daylight). Therefore, wall clock time from 1:00 AM to 1:59 AM do not exist on 136 * In this example, 1:30 AM is interpreted as 1:30 AM standard time (non-exist), 137 * so the final result will be 2:30 AM daylight time. 140 * hour at 2:00 AM. So wall clock time from 1:00 AM to 1:59 AM occu 288 AM, enumerator in enum:Calendar::EAmpm [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 146 // Try to fold more of the base or index of AM into AM, where IsBase 148 bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const; 150 // Try to describe N in AM, returning true on success. 151 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const; 153 // Extract individual target operands from matched address AM. 154 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 156 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT, 361 // Change the base or index in AM to Value, where IsBase selects 363 static void changeComponent(SystemZAddressingMode &AM, boo argument 374 expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, SDValue Value) argument 386 expandIndex(SystemZAddressingMode &AM, SDValue Base, SDValue Index) argument 398 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument 413 expandAddress(SystemZAddressingMode &AM, bool IsBase) const argument 575 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp) const argument 600 getAddressOperands(const SystemZAddressingMode &AM, EVT VT, SDValue &Base, SDValue &Disp, SDValue &Index) const argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 905 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 906 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 679 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 682 if (AM != ISD::UNINDEXED) { 819 ISD::MemIndexedMode AM = ST->getAddressingMode(); local 822 if (AM != ISD::UNINDEXED) {
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H A D | HexagonISelLowering.cpp | 656 ISD::MemIndexedMode &AM, 681 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1630 /// AM is legal for this target, for a load/store of the specified type. 1631 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1634 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 1639 if (AM.BaseGV) { 1643 int Scale = AM.Scale; 653 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1908 /// by AM is legal for this target, for a load/store of the specified type. 1910 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1913 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1917 if (AM.BaseGV) { 1918 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1919 AM.BaseOffs%4 == 0; 1925 if (AM [all...] |
/external/chromium_org/third_party/libaddressinput/src/java/src/com/android/i18n/addressinput/ |
H A D | RegionDataConstants.java | 65 AM(new String[]{ enum constant in enum:RegionDataConstants.RegionDataEnum
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 806 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 809 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 842 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 845 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 862 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 865 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 937 ISD::MemIndexedMode AM local 1024 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); local 1343 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 1444 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 1517 ISD::MemIndexedMode AM = LD->getAddressingMode(); local [all...] |