/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 238 uint64_t Amount = Old->getOperand(0).getImm(); local 239 if (Amount != 0) { 243 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; 249 .addReg(MSP430::SPW).addImm(Amount); 254 Amount -= CalleeAmt; 255 if (Amount) 258 .addReg(MSP430::SPW).addImm(Amount);
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 151 int64_t Amount = I->getOperand(0).getImm(); local 154 Amount = -Amount; 159 TII.adjustStackPtr(Mips::SP, Amount, MBB, I);
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H A D | Mips16InstrInfo.cpp | 258 // Adjust SP by Amount bytes where bytes can be up to 32bit number. 263 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, argument 279 MIB1.addImm(Amount).addImm(-1); 290 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, argument 296 /// Adjust SP by Amount bytes. 297 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, argument 300 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16> 301 BuildAddiuSpImm(MBB, I, Amount); 303 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I); 464 int64_t Amount) { 463 validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount) argument [all...] |
H A D | MipsSEFrameLowering.cpp | 499 int64_t Amount = I->getOperand(0).getImm(); local 502 Amount = -Amount; 505 TII.adjustStackPtr(SP, Amount, MBB, I);
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H A D | MipsSEInstrInfo.cpp | 359 /// Adjust SP by Amount bytes. 360 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, argument 368 if (isInt<16>(Amount))// addi sp, sp, amount 369 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 371 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.c | 53 float Amount; member in struct:count_inst 167 count_inst->Amount += amount; 174 count_inst->Amount -= amount; 232 count_inst.Amount = 0.0f; 272 if(count_inst.Amount == 0.0f){ 275 DBG("Counter is increased by %f each iteration.\n", count_inst.Amount); 289 count_inst.Amount); 295 count_inst.Amount) + 1;
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 64 unsigned Amount = Old->getOperand(0).getImm(); local 65 if (Amount != 0) { 70 Amount = (Amount+Align-1)/Align*Align; 75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
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H A D | ARMFrameLowering.cpp | 1638 unsigned Amount = Old->getOperand(0).getImm(); local 1639 if (Amount != 0) { 1644 Amount = (Amount+Align-1)/Align*Align; 1659 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, 1665 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.c | 53 float Amount; member in struct:count_inst 167 count_inst->Amount += amount; 174 count_inst->Amount -= amount; 232 count_inst.Amount = 0.0f; 272 if(count_inst.Amount == 0.0f){ 275 DBG("Counter is increased by %f each iteration.\n", count_inst.Amount); 289 count_inst.Amount); 295 count_inst.Amount) + 1;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 122 int64_t Amount = I->getOperand(0).getImm(); local 123 Amount = RoundUpToAlignment(Amount, Align); 125 Amount = -Amount; 141 assert(Amount > -0xffffff && Amount < 0xffffff && "call frame too large"); 142 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 487 uint64_t Amount = Old->getOperand(0).getImm(); local 488 if (Amount != 0) { 493 Amount = (Amount+Align-1)/Align*Align; 495 assert(Amount%4 == 0); 496 Amount /= 4; 498 bool isU6 = isImmU6(Amount); 499 if (!isU6 && !isImmU16(Amount)) { 503 << Amount << "\n"; 512 .addImm(Amount); [all...] |
/external/llvm/include/llvm/Analysis/ |
H A D | BlockFrequencyInfoImpl.h | 335 uint64_t Amount; member in struct:llvm::BlockFrequencyInfoImplBase::Weight 336 Weight() : Type(Local), Amount(0) {} 354 void addLocal(const BlockNode &Node, uint64_t Amount) { argument 355 add(Node, Amount, Weight::Local); 357 void addExit(const BlockNode &Node, uint64_t Amount) { argument 358 add(Node, Amount, Weight::Exit); 360 void addBackedge(const BlockNode &Node, uint64_t Amount) { argument 361 add(Node, Amount, Weight::Backedge); 376 void add(const BlockNode &Node, uint64_t Amount, Weight::DistType Type);
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/external/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 1202 /// isUndefShift - Returns true if a shift by \c Amount always yields undef. 1203 static bool isUndefShift(Value *Amount) { argument 1204 Constant *C = dyn_cast<Constant>(Amount);
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 227 unsigned Amount; member in struct:__anon25952::AArch64Operand::ShiftExtendOp 398 return ShiftExtend.Amount; 1701 Op->ShiftExtend.Amount = Val;
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 4651 unsigned &Amount) { 4673 Amount = 0; 4703 Amount = Imm; 7403 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); local 7404 if (Amount == 32) Amount = 0; 7412 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 4650 parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, unsigned &Amount) argument
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