| /external/llvm/lib/MC/ |
| H A D | MCCodeGenInfo.cpp | 18 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, argument
21 CMModel = CM;
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| /external/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 27 Reloc::Model RM, CodeModel::Model CM,
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 70 CodeModel::Model CM,
75 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
69 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 30 Reloc::Model RM, CodeModel::Model CM,
32 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUTargetMachine.cpp | 44 Reloc::Model RM, CodeModel::Model CM,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | BoolAssignmentChecker.cpp | 81 ConstraintManager &CM = C.getConstraintManager(); local
99 std::tie(stateGE, stateLT) = CM.assumeDual(state, *greaterThanEqualToZero);
135 std::tie(stateLE, stateGT) = CM.assumeDual(state, *lessThanEqToOne);
|
| H A D | NonNullParamChecker.cpp | 124 ConstraintManager &CM = C.getConstraintManager(); local
126 std::tie(stateNotNull, stateNull) = CM.assumeDual(state, *DV);
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 70 Reloc::Model RM, CodeModel::Model CM,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
67 HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 54 CodeModel::Model CM,
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 55 StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
54 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 31 Reloc::Model RM, CodeModel::Model CM,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
86 CodeModel::Model CM,
88 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
98 CodeModel::Model CM,
100 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
81 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
93 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 25 Reloc::Model RM, CodeModel::Model CM,
27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 26 Reloc::Model RM, CodeModel::Model CM,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUTargetMachine.cpp | 44 Reloc::Model RM, CodeModel::Model CM,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 57 CodeModel::Model CM,
60 X->InitMCCodeGenInfo(RM, CM, OL);
56 createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 73 Reloc::Model RM, CodeModel::Model CM,
76 CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
70 LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 87 Reloc::Model RM, CodeModel::Model CM,
90 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
100 Reloc::Model RM, CodeModel::Model CM,
102 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
109 Reloc::Model RM, CodeModel::Model CM,
111 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
84 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian) argument
98 AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
107 AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 81 CodeModel::Model CM,
87 if (CM == CodeModel::Default)
88 CM = CodeModel::Small;
92 else if (CM == CodeModel::JITDefault)
93 CM = CodeModel::Large;
94 else if (CM != CodeModel::Small && CM != CodeModel::Large)
108 X->InitMCCodeGenInfo(RM, CM, OL);
80 createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 51 Reloc::Model RM, CodeModel::Model CM,
53 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
75 Reloc::Model RM, CodeModel::Model CM,
77 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
89 Reloc::Model RM, CodeModel::Model CM,
91 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
98 Reloc::Model RM, CodeModel::Model CM,
100 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
107 Reloc::Model RM, CodeModel::Model CM,
109 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, O
48 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
73 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
86 ARMLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
95 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
104 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
116 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
125 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 56 Reloc::Model RM, CodeModel::Model CM,
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
68 Reloc::Model RM, CodeModel::Model CM,
70 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
77 Reloc::Model RM, CodeModel::Model CM,
79 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
53 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
66 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
75 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 72 Reloc::Model RM, CodeModel::Model CM,
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
83 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
91 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
69 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
81 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
89 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 42 Reloc::Model RM, CodeModel::Model CM,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
54 Reloc::Model RM, CodeModel::Model CM,
56 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
64 Reloc::Model RM, CodeModel::Model CM,
66 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
40 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
51 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
61 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUTargetMachine.cpp | 69 Reloc::Model RM, CodeModel::Model CM,
73 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
66 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 58 CodeModel::Model CM,
61 X->InitMCCodeGenInfo(RM, CM, OL);
57 createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 129 CodeModel::Model CM,
167 if (CM == CodeModel::Default)
168 CM = CodeModel::Small;
169 else if (CM == CodeModel::JITDefault)
170 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
171 X->InitMCCodeGenInfo(RM, CM, OL);
128 createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|