/external/clang/test/SemaTemplate/ |
H A D | value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) { argument 6 return Cond? "honk" : N; 9 const char *f1(bool Cond) { argument 10 return Cond? N : "honk";
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H A D | constructor-template.cpp | 60 X2 test(bool Cond, X2 x2) { argument 61 if (Cond) 80 X4 test_X4(bool Cond, X4 x4) { argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.h | 12 struct rc_instruction * Cond; member in struct:loop_info
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_emulate_loops.h | 12 struct rc_instruction * Cond; member in struct:loop_info
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ConstraintManager.h | 68 DefinedSVal Cond, 75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { argument 76 ProgramStateRef StTrue = assume(State, Cond, true); 78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary 86 assert(assume(State, Cond, false) && "System is over constrained."); 91 ProgramStateRef StFalse = assume(State, Cond, false);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64A53Fix835769.cpp | 136 SmallVector<MachineOperand, 2> Cond; local 140 if (S == PrevBB && !TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond) &&
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H A D | AArch64BranchRelaxation.cpp | 407 SmallVector<MachineOperand, 2> Cond; local 408 TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, false);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430BranchSelector.cpp | 151 SmallVector<MachineOperand, 1> Cond; local 152 Cond.push_back(I->getOperand(1)); 155 TII->ReverseBranchCondition(Cond); 157 .addImm(4).addOperand(Cond[0]);
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H A D | MSP430InstrInfo.cpp | 130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 157 Cond[0].setImm(CC); 175 SmallVectorImpl<MachineOperand> &Cond, 210 Cond.clear(); 234 if (Cond.empty()) { 237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 243 assert(Cond.size() == 1); 251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[ 172 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 263 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 172 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { 189 Cond.push_back(LastInst->getOperand(0)); 207 Cond.push_back(SecondLastInst->getOperand(0)); 253 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { 256 assert((Cond.size() == 1 || Cond.size() == 0) && 261 if (Cond.empty()) // Unconditional branch 264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) 270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); 170 AnalyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 251 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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/external/llvm/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 207 Value *Cond = SI->getCondition(); local 212 if (isa<Instruction>(Cond) && cast<Instruction>(Cond)->getParent() == BB) 232 Cond, Case, *PI, BB); 261 Cond = SI->getCondition();
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 445 SDValue Cond = (isZero(LHS) ? RHS : LHS); 463 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC); local 492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32, 493 DAG.getNode(ISD::FNEG, DL, VT, Cond)); 496 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 501 SDValue Cond; local 507 Cond = DAG.getNode( 515 Cond = DAG.getNode( 520 Cond); [all...] |
H A D | SIISelLowering.cpp | 384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); local 385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
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H A D | AMDILISelLowering.cpp | 477 SDValue Cond = Op.getOperand(1); local 484 Chain, Jump, Cond);
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H A D | R600InstrInfo.cpp | 180 SmallVectorImpl<MachineOperand> &Cond, 216 Cond.push_back(predSet->getOperand(1)); 217 Cond.push_back(predSet->getOperand(2)); 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 240 Cond.push_back(predSet->getOperand(1)); 241 Cond.push_back(predSet->getOperand(2)); 242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); 264 const SmallVectorImpl<MachineOperand> &Cond, 270 if (Cond.empty()) { 277 PredSet->getOperand(2).setImm(Cond[ 177 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | CheckerDocumentation.cpp | 208 SVal Cond, 207 evalAssume(ProgramStateRef State, SVal Cond, bool Assumption) const argument
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | SimpleConstraintManager.cpp | 69 DefinedSVal Cond, 72 if (Optional<Loc> LV = Cond.getAs<Loc>()) { 81 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); 84 return assume(state, Cond.castAs<NonLoc>(), Assumption); 115 NonLoc Cond, 120 if (!canReasonAbout(Cond)) { 122 SymbolRef sym = Cond.getAsSymExpr(); 126 switch (Cond.getSubKind()) { 131 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); 182 bool b = Cond 68 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument 114 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument [all...] |
/external/clang/test/SemaCXX/ |
H A D | vector.cpp | 40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, argument 43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; 44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; 45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; 46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; 49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; 50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; 51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; 52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; 55 (void)(Cond 108 test_implicit_conversions(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, longlong16_e ll16e, convertible_to<char16> to_c16, convertible_to<longlong16> to_ll16, convertible_to<char16_e> to_c16e, convertible_to<longlong16_e> to_ll16e, convertible_to<char16&> rto_c16, convertible_to<char16_e&> rto_c16e) argument [all...] |
/external/deqp/modules/glshared/ |
H A D | glsAttributeLocationTests.hpp | 60 class Cond class in namespace:deqp::gls::AttributeLocationTestUtil 69 Cond (ConstCond cond); 70 explicit Cond (const std::string& name, bool negate = true); 71 bool operator== (const Cond& other) const { return m_negate == other.m_negate && m_name == other.m_name; } 72 bool operator!= (const Cond& other) const { return !(*this == other); } 99 const Cond& cond = Cond::COND_ALWAYS, 105 const Cond& getCondition (void) const { return m_cond; } 112 Cond m_cond;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const { 80 Cond.push_back(MachineOperand::CreateImm(Opc)); 83 Cond.push_back(Inst->getOperand(i)); 89 SmallVectorImpl<MachineOperand> &Cond, 92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 99 const SmallVectorImpl<MachineOperand>& Cond) 101 unsigned Opc = Cond[0].getImm(); 105 for (unsigned i = 1; i < Cond.size(); ++i) { 106 if (Cond[i].isReg()) 107 MIB.addReg(Cond[ 86 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 117 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument 184 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr*> &BranchInstrs) const argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIAnnotateControlFlow.cpp | 83 Value *handleLoopCondition(Value *Cond, PHINode *Broken); 206 Value *SIAnnotateControlFlow::handleLoopCondition(Value *Cond, PHINode *Broken) { argument 207 if (PHINode *Phi = dyn_cast<PHINode>(Cond)) { 250 } else if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { 253 Value *Args[] = { Cond, Broken }; 267 Value *Cond = Term->getCondition(); local 269 Value *Arg = handleLoopCondition(Cond, Broken);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 131 SmallVectorImpl<MachineOperand> &Cond, 163 Cond.clear(); 184 if (Cond.empty()) { 220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 233 const SmallVectorImpl<MachineOperand> &Cond, 236 assert((Cond.size() == 1 || Cond.size() == 0) && 239 if (Cond.empty()) { 246 unsigned CC = Cond[0].getImm(); 128 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 231 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 196 SmallVectorImpl<MachineOperand> &Cond, 229 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 230 Cond.push_back(LastInst->getOperand(0)); 251 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 252 Cond.push_back(SecondLastInst->getOperand(0)); 284 const SmallVectorImpl<MachineOperand> &Cond, 288 assert((Cond.size() == 2 || Cond.size() == 0) && 292 if (Cond.empty()) { 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[ 194 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 282 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 445 SDValue Cond = (isZero(LHS) ? RHS : LHS); 463 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC); local 492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32, 493 DAG.getNode(ISD::FNEG, DL, VT, Cond)); 496 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 501 SDValue Cond; local 507 Cond = DAG.getNode( 515 Cond = DAG.getNode( 520 Cond); [all...] |
H A D | SIISelLowering.cpp | 384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); local 385 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
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