/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.h | 36 const ScheduleDAG *DAG) 37 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), 35 ARMHazardRecognizer(const InstrItineraryData *ItinData, const ScheduleDAG *DAG) argument
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H A D | ARMSelectionDAGInfo.cpp | 28 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, argument 35 const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget<ARMSubtarget>(); 67 Loads[i] = DAG.getLoad(VT, dl, Chain, 68 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 69 DAG.getConstant(SrcOff, MVT::i32)), 75 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 80 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 81 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 82 DAG.getConstant(DstOff, MVT::i32)), 87 Chain = DAG 148 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument [all...] |
/external/clang/test/CodeGenCXX/ |
H A D | debug-info-byval.cpp | 5 class DAG { class
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.cpp | 29 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, argument
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H A D | HexagonMachineScheduler.h | 103 /// Perform platform-specific DAG postprocessing. 134 VLIWMachineScheduler *DAG; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary 156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"), 168 DAG = dag; 191 VLIWMachineScheduler *DAG; member in class:llvm::ConvergingVLIWScheduler 207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG; member in class:llvm::PPCDispatchGroupSBHazardRecognizer 37 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), 57 const ScheduleDAG &DAG; member in class:llvm::PPCHazardRecognizer970 78 PPCHazardRecognizer970(const ScheduleDAG &DAG);
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H A D | PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 163 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 184 DEBUG(DAG->dumpNode(SU)); 223 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 262 PPCHazardRecognizer970::PPCHazardRecognizer970(const ScheduleDAG &DAG) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ScoreboardHazardRecognizer.h | 95 const ScheduleDAG *DAG; member in class:llvm::ScoreboardHazardRecognizer 108 const ScheduleDAG *DAG,
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers. 39 SelectionDAG *DAG; // DAG of the current basic block member in class:llvm::ScheduleDAGSDNodes
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H A D | LegalizeTypes.h | 1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===// 36 SelectionDAG &DAG; member in class:llvm::DAGTypeLegalizer 67 return TLI.getTypeAction(*DAG.getContext(), VT); 72 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal; 76 return TLI.getSetCCResultType(*DAG.getContext(), VT); 123 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 141 SelectionDAG &getDAG() const { return DAG; } 203 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, 204 DAG.getValueType(OldVT)); 213 return DAG [all...] |
H A D | ScheduleDAGSDNodes.cpp | 50 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr), 57 DAG = dag; 59 // Clear the scheduler's SUnit DAG. 80 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 136 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, argument 146 SDVTList VTList = DAG->getVTList(VTs); 156 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); 163 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { argument 184 CloneNodeWithValues(N, DAG, VTs, Glue); 191 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) { argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64SelectionDAGInfo.cpp | 25 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, 33 ? DAG.getTarget().getSubtarget<AArch64Subtarget>().getBZeroEntry() 40 DAG.getTarget().getTargetLowering()); 43 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 51 TargetLowering::CallLoweringInfo CLI(DAG); 53 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), 54 DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args), 0) 24 EmitTargetCodeForMemset( SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.cpp | 26 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, argument 35 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { 36 const TargetLowering &TLI = *DAG.getTarget().getTargetLowering(); 39 Entry.Ty = TLI.getDataLayout()->getIntPtrType(*DAG.getContext()); 44 TargetLowering::CallLoweringInfo CLI(DAG); 47 Type::getVoidTy(*DAG.getContext()), 48 DAG.getExternalSymbol("__memcpy_4", TLI.getPointerTy()),
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/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, argument 104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, argument 118 EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc dl, SDValue Chain, argument 131 EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 145 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, argument 154 EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 160 EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument
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/external/llvm/lib/Target/R600/ |
H A D | R600MachineScheduler.h | 29 const ScheduleDAGMILive *DAG; member in class:llvm::R600SchedStrategy 71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 53 DebugLoc DL, SelectionDAG &DAG, 70 DebugLoc DL, SelectionDAG &DAG) const 72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 88 // AMDIL DAG lowering 89 case ISD::SDIV: return LowerSDIV(Op, DAG); 90 case ISD::SREM: return LowerSREM(Op, DAG); 91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument [all...] |
H A D | AMDGPUInstrInfo.cpp | 173 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument
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H A D | R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===// 10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file 239 // Custom DAG Lowering Operations 245 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const 248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 249 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 250 case ISD::ROTL: return LowerROTL(Op, DAG); 251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 252 case ISD::SETCC: return LowerSETCC(Op, DAG); 259 MachineFunction &MF = DAG 357 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument [all...] |
H A D | SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===// 10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is 258 // Custom DAG Lowering Operations 261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const 264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 265 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 266 case ISD::LOAD: return LowerLOAD(Op, DAG); 267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND); 275 return CreateLiveInRegister(DAG, 293 Loweri1ContextSwitch(SDValue Op, SelectionDAG &DAG, unsigned VCCNode) const argument 394 SelectionDAG &DAG = DCI.DAG; local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 32 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, argument 48 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, 49 DAG.getConstant(Size, PtrVT), 50 DAG.getConstant(Size / 256, PtrVT)); 51 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, 52 DAG.getConstant(Size, PtrVT)); 56 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 65 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, 73 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, argument 80 return DAG 86 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dst, SDValue Byte, SDValue Size, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo) const argument 158 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument 182 addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) argument 192 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 207 EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const argument 237 EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const argument 248 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 265 getBoundedStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue Limit) argument 278 EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const argument 285 EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 33 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, argument 40 const X86Subtarget &Subtarget = DAG.getTarget().getSubtarget<X86Subtarget>(); 56 EVT IntPtr = DAG.getTargetLoweringInfo().getPointerTy(); 57 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 66 TargetLowering::CallLoweringInfo CLI(DAG); 68 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), 69 DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args), 73 std::pair<SDValue,SDValue> CallResult = DAG.getTargetLoweringInfo().LowerCallTo(CLI); 113 Count = DAG.getIntPtrConstant(SizeVal); 119 Count = DAG 176 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// 53 DebugLoc DL, SelectionDAG &DAG, 70 DebugLoc DL, SelectionDAG &DAG) const 72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) 88 // AMDIL DAG lowering 89 case ISD::SDIV: return LowerSDIV(Op, DAG); 90 case ISD::SREM: return LowerSREM(Op, DAG); 91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 48 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument [all...] |
H A D | AMDGPUInstrInfo.cpp | 173 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, argument
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H A D | R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===// 10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file 239 // Custom DAG Lowering Operations 245 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const 248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 249 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 250 case ISD::ROTL: return LowerROTL(Op, DAG); 251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 252 case ISD::SETCC: return LowerSETCC(Op, DAG); 259 MachineFunction &MF = DAG 357 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument [all...] |
H A D | SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===// 10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is 258 // Custom DAG Lowering Operations 261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const 264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 265 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 266 case ISD::LOAD: return LowerLOAD(Op, DAG); 267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND); 275 return CreateLiveInRegister(DAG, 293 Loweri1ContextSwitch(SDValue Op, SelectionDAG &DAG, unsigned VCCNode) const argument 394 SelectionDAG &DAG = DCI.DAG; local [all...] |