Searched defs:DefIdx (Results 1 - 17 of 17) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h136 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter
154 return DefIdx-1;
/external/llvm/lib/CodeGen/
H A DLiveRangeCalc.cpp90 unsigned DefIdx; local
94 } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
97 if (MI->getOperand(DefIdx).isEarlyClobber())
H A DTargetSchedule.cpp129 unsigned DefIdx = 0; local
133 ++DefIdx;
135 return DefIdx;
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local
190 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
193 STI->getWriteLatencyEntry(SCDesc, DefIdx);
209 // If DefIdx does not exist in the model (e.g. implicit defs), then return
217 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
241 for (unsigned DefIdx
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H A DPeepholeOptimizer.cpp166 unsigned DefIdx; member in class:__anon25783::ValueTracker
205 /// at the operand index \p DefIdx.
212 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, argument
215 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
217 assert(Def->getOperand(DefIdx).isDef() &&
218 Def->getOperand(DefIdx).isReg() &&
221 Reg = Def->getOperand(DefIdx).getReg();
462 unsigned SrcIdx, DefIdx; local
465 SrcIdx, DefIdx) !
486 getCopyOrBitcastDefUseIdx(const MachineInstr &Copy, unsigned &DefIdx, unsigned &SrcIdx) argument
532 unsigned DefIdx, SrcIdx; local
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H A DRegAllocFast.cpp736 unsigned DefIdx = 0; local
737 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
739 << DefIdx << ".\n"); local
H A DTargetInstrInfo.cpp702 SDNode *DefNode, unsigned DefIdx,
712 return ItinData->getOperandCycle(DefClass, DefIdx);
714 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
778 unsigned DefIdx) const {
783 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
791 const MachineInstr *DefMI, unsigned DefIdx,
795 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
824 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
828 const MachineInstr *DefMI, unsigned DefIdx,
839 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseM
701 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
790 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
827 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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H A DInlineSpiller.cpp908 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM, local
910 (void)DefIdx;
911 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
912 << *LIS.getInstructionFromIndex(DefIdx));
H A DMachineLICM.cpp201 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
1011 unsigned DefIdx, unsigned Reg) const {
1028 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i))
1010 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
H A DMachineInstr.cpp720 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); local
721 if (DefIdx != -1)
722 tieOperands(DefIdx, OpNo);
983 unsigned DefIdx; local
984 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
985 OpIdx = DefIdx;
1165 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1177 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument
1178 MachineOperand &DefMO = getOperand(DefIdx);
1180 assert(DefMO.isDef() && "DefIdx mus
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H A DMachineVerifier.cpp888 unsigned DefIdx; local
890 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
891 Reg != MI->getOperand(DefIdx).getReg())
1084 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); local
1085 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1088 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1090 if (VNI->def != DefIdx) {
1093 << DefIdx << " in " << LI << '\n';
1097 *OS << DefIdx << " i
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H A DRegisterCoalescer.cpp597 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); local
598 assert(DefIdx != -1);
600 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
699 SlotIndex DefIdx = UseIdx.getRegSlot(); local
700 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
703 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
704 assert(DVNI->def == DefIdx);
/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h195 /// index DefIdx can be bypassed when it's read by an instruction of
197 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument
201 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
203 if (Forwardings[FirstDefIdx + DefIdx] == 0)
211 return Forwardings[FirstDefIdx + DefIdx] ==
218 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument
223 int DefCycle = getOperandCycle(DefClass, DefIdx);
233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h838 SDNode *DefNode, unsigned DefIdx,
850 const MachineInstr *DefMI, unsigned DefIdx,
857 const MachineInstr *DefMI, unsigned DefIdx,
892 const MachineInstr *DefMI, unsigned DefIdx,
901 const MachineInstr *DefMI, unsigned DefIdx) const;
890 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp109 const MachineInstr *DefMI, unsigned DefIdx,
112 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
115 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
108 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp3345 unsigned DefIdx = 0; local
3349 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3350 IsTiedToChangedOp = OpChanged[DefIdx];
3426 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
H A DARMBaseInstrInfo.cpp3008 unsigned DefIdx, unsigned DefAlign) const {
3009 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3012 return ItinData->getOperandCycle(DefClass, DefIdx);
3049 unsigned DefIdx, unsigned DefAlign) const {
3050 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3053 return ItinData->getOperandCycle(DefClass, DefIdx);
3152 unsigned DefIdx, unsigned DefAlign,
3158 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3159 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3168 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3005 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3046 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument
3150 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3261 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3497 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
3588 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument
3891 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp5392 const MachineInstr *DefMI, unsigned DefIdx,
5390 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument

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