/external/llvm/bindings/ocaml/linker/ |
H A D | linker_ocaml.c | 47 CAMLprim value llvm_link_modules(LLVMModuleRef Dst, LLVMModuleRef Src, value Mode) { argument 50 if (LLVMLinkModules(Dst, Src, Int_val(Mode), &Message))
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
H A D | radeon_variable.h | 46 struct rc_dst_register Dst; member in struct:rc_variable
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/external/clang/lib/Analysis/ |
H A D | CFGReachabilityAnalysis.cpp | 26 const CFGBlock *Dst) { 28 const unsigned DstBlockID = Dst->getBlockID(); 32 mapReachability(Dst); 42 void CFGReverseBlockReachabilityAnalysis::mapReachability(const CFGBlock *Dst) { argument 46 ReachableSet &DstReachability = reachable[Dst->getBlockID()]; 51 worklist.push_back(Dst); 61 // Update reachability information for this node -> Dst 63 // Don't insert Dst -> Dst unless it was a predecessor of itself 25 isReachable(const CFGBlock *Src, const CFGBlock *Dst) argument
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/external/llvm/include/llvm/Target/ |
H A D | CostTable.h | 51 TypeTy Dst; member in struct:llvm::TypeConversionCostTblEntry 60 unsigned len, int ISD, CompareTy Dst, 63 if (ISD == Tbl[i].ISD && Src == Tbl[i].Src && Dst == Tbl[i].Dst) 74 int ISD, CompareTy Dst, CompareTy Src) { member in namespace:llvm 75 return ConvertCostTableLookup(Tbl, N, ISD, Dst, Src); 59 ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, CompareTy Dst, CompareTy Src) argument
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/external/llvm/include/llvm/Transforms/Utils/ |
H A D | BasicBlockUtils.h | 116 /// SplitCriticalEdge - If an edge from Src to Dst is critical, split the edge 120 inline BasicBlock *SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst, argument 128 if (TI->getSuccessor(i) == Dst)
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_variable.h | 46 struct rc_dst_register Dst; member in struct:rc_variable
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.cpp | 30 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, 29 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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H A D | HexagonPeephole.cpp | 104 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src); 140 MachineOperand &Dst = MI->getOperand(0); local 142 unsigned DstReg = Dst.getReg(); 159 MachineOperand &Dst = MI->getOperand(0); local 164 unsigned DstReg = Dst.getReg(); 176 MachineOperand &Dst = MI->getOperand(0); local 181 unsigned DstReg = Dst.getReg(); 191 MachineOperand &Dst = MI->getOperand(0); local 193 unsigned DstReg = Dst.getReg(); 209 MachineOperand &Dst local 314 ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) argument [all...] |
/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUAsmBackend.cpp | 76 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); local 78 *Dst = (Value - 4) / 4;
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/external/llvm/lib/Support/ |
H A D | ConvertUTFWrapper.cpp | 114 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]); local 115 UTF8 *DstEnd = Dst + Out.size(); 118 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 126 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64SelectionDAGInfo.cpp | 25 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, 46 Entry.Node = Dst; 24 EmitTargetCodeForMemset( SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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H A D | AArch64AdvSIMDScalarPass.cpp | 229 unsigned Dst = MI->getOperand(0).getReg(); local 232 Use = MRI->use_instr_nodbg_begin(Dst), 265 unsigned Dst, unsigned Src, bool IsKill) { 268 Dst) 333 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); local 338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst) 345 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true); 264 insertCopy(const AArch64InstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill) argument
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H A D | AArch64TargetTransformInfo.cpp | 109 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const 295 unsigned AArch64TTI::getCastInstrCost(unsigned Opcode, Type *Dst, argument 301 EVT DstTy = TLI->getValueType(Dst); 304 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 375 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.cpp | 27 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, 40 Entry.Node = Dst; Args.push_back(Entry); 26 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineObjC.cpp | 24 ExplodedNodeSet &Dst) { 35 // the created nodes in 'Dst'. 36 getCheckerManager().runCheckersForPostStmt(Dst, dstIvar, Ex, *this); 41 ExplodedNodeSet &Dst) { 42 getCheckerManager().runCheckersForPreStmt(Dst, Pred, S, *this); 47 ExplodedNodeSet &Dst) { 132 getCheckerManager().runCheckersForPostStmt(Dst, Tmp, S, *this); 137 ExplodedNodeSet &Dst) { 212 // the created nodes in 'Dst'. 213 getCheckerManager().runCheckersForPostObjCMessage(Dst, dstPostvisi 22 VisitLvalObjCIvarRefExpr(const ObjCIvarRefExpr *Ex, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument 39 VisitObjCAtSynchronizedStmt(const ObjCAtSynchronizedStmt *S, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument 45 VisitObjCForCollectionStmt(const ObjCForCollectionStmt *S, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument 135 VisitObjCMessage(const ObjCMessageExpr *ME, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument [all...] |
/external/eigen/test/ |
H A D | vectorization_logic.cpp | 31 template<typename Dst, typename Src> 32 bool test_assign(const Dst&, const Src&, int traversal, int unrolling) argument 34 internal::assign_traits<Dst,Src>::debug(); 35 bool res = internal::assign_traits<Dst,Src>::Traversal==traversal 36 && internal::assign_traits<Dst,Src>::Unrolling==unrolling; 40 << " got " << demangle_traversal(internal::assign_traits<Dst,Src>::Traversal) << "\n"; 42 << " got " << demangle_unrolling(internal::assign_traits<Dst,Src>::Unrolling) << "\n"; 47 template<typename Dst, typename Src> 50 internal::assign_traits<Dst,Src>::debug(); 51 bool res = internal::assign_traits<Dst,Sr [all...] |
/external/llvm/lib/IR/ |
H A D | GCOV.cpp | 156 uint32_t Dst; local 157 if (!Buff.readInt(Dst)) return false; 158 Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst])); 161 Blocks[Dst]->addSrcEdge(Edge); 335 if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges()) 336 DstEdges[DstEdgeNo]->Dst.Counter += N; 371 dbgs() << Edge->Dst.Number << " (" << Edge->Count << "), ";
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H A D | IRBuilder.cpp | 82 CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Align, argument 84 Dst = getCastedInt8PtrValue(Dst); 87 Value *Ops[] = { Dst, Src, Size, getInt32(Align), getInt1(isVolatile) }; 88 Type *Tys[] = { Dst->getType(), Src->getType(), Size->getType() }; 106 CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Align, argument 108 Dst = getCastedInt8PtrValue(Dst); 111 Value *Ops[] = { Dst, Src, Size, getInt32(Align), getInt1(isVolatile) }; 112 Type *Tys[] = { Dst [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 30 SDValue Dst, SDValue Src, 81 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 133 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 149 SDValue Chain, SDValue Dst, 166 Entry.Node = Dst; 28 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 148 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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H A D | ARMTargetTransformInfo.cpp | 117 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 183 unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst, argument 205 EVT DstTy = TLI->getValueType(Dst); 208 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 379 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 112 const MCOperand &Dst = MI->getOperand(0); local 122 printRegName(O, Dst.getReg()); 135 const MCOperand &Dst = MI->getOperand(0); local 144 printRegName(O, Dst.getReg());
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/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
H A D | tgsi_parse.h | 99 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS]; member in struct:tgsi_full_instruction
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/tests/ |
H A D | rc_test_helpers.c | 287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n", 299 struct match_info Dst; member in struct:inst_tokens 353 tokens.Dst.String = inst_str + matches[3].rm_so; 354 tokens.Dst.Length = match_length(matches, 3); 357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1)); 358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length); 359 dst_str[tokens.Dst.Length] = '\0';
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ExprEngine.h | 113 /// of the function are added into the Dst set, which represent the exit 118 ExplodedNodeSet &Dst) { 119 return Engine.ExecuteWorkListWithInitialState(L, Steps, InitState, Dst); 206 ExplodedNode *Pred, ExplodedNodeSet &Dst); 208 ExplodedNode *Pred, ExplodedNodeSet &Dst); 210 ExplodedNode *Pred, ExplodedNodeSet &Dst); 212 ExplodedNode *Pred, ExplodedNodeSet &Dst); 214 ExplodedNode *Pred, ExplodedNodeSet &Dst); 226 ExplodedNodeSet &Dst, 235 ExplodedNodeSet &Dst, 116 ExecuteWorkListWithInitialState(const LocationContext *L, unsigned Steps, ProgramStateRef InitState, ExplodedNodeSet &Dst) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 234 /// Move NumOps operands from Src to Dst, updating use-def lists as needed. 236 /// The Dst range is assumed to be uninitialized memory. (Or it may contain 240 /// The Src and Dst ranges may overlap. 241 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, argument 244 assert(Src != Dst && NumOps && "Noop moveOperands"); 246 // Copy backwards if Dst is within the Src range. 248 if (Dst >= Src && Dst < Src + NumOps) { 250 Dst += NumOps - 1; 256 new (Dst) MachineOperan [all...] |