Searched defs:DstRC (Results 1 - 9 of 9) sorted by relevance
/external/llvm/lib/Target/R600/ |
H A D | SILowerI1Copies.cpp | 111 const TargetRegisterClass *DstRC = local 116 if (DstRC == &AMDGPU::VReg_1RegClass && 129 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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H A D | SIFixSGPRCopies.cpp | 184 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); local 188 DstRC == &AMDGPU::M0RegRegClass || 193 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); 262 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local 263 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); 266 if (TRI->isSGPRClass(DstRC) &&
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H A D | SIInstrInfo.cpp | 990 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local 992 if (DstRC != Src0RC) { 994 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; local 161 DstRC = MRI->getRegClass(VRBase); 164 DstRC = UseRC; 166 DstRC = TLI->getRegClassFor(VT); 175 VRBase = MRI->createVirtualRegister(DstRC); 329 const TargetRegisterClass *DstRC = nullptr; 331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 332 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 333 unsigned NewVReg = MRI->createVirtualRegister(DstRC); [all...] |
/external/llvm/lib/CodeGen/ |
H A D | PeepholeOptimizer.cpp | 279 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local 280 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); 281 if (!DstRC) 388 MRI->constrainRegClass(DstReg, DstRC);
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H A D | RegisterCoalescer.cpp | 291 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local 299 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, 306 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 310 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); 313 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 328 CrossClass = NewRC != DstRC || NewRC != SrcRC;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 1954 const TargetRegisterClass *DstRC = local 1962 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 2037 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); local 2038 unsigned ResultReg = createResultReg(DstRC); 2057 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); local 2059 unsigned ResultReg = createResultReg(DstRC);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 4694 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); local 4699 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4766 const TargetRegisterClass *DstRC = nullptr; local 4768 DstRC = getRegClass(MCID, 0, &RI, MF); 4769 VTs.push_back(*DstRC->vt_begin()); 4800 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
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