Searched defs:ExtType (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1143 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); local
1144 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
H A DAArch64ISelDAGToDAG.cpp913 ISD::LoadExtType ExtType = LD->getExtensionType(); local
918 if (ExtType == ISD::NON_EXTLOAD)
920 else if (ExtType == ISD::SEXTLOAD)
930 if (ExtType == ISD::SEXTLOAD) {
943 if (ExtType == ISD::SEXTLOAD) {
H A DAArch64ISelLowering.cpp1769 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; local
1779 ExtType = ISD::SEXTLOAD;
1782 ExtType = ISD::ZEXTLOAD;
1785 ExtType = ISD::EXTLOAD;
1789 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
6965 unsigned ExtType = LHS.getOpcode(); local
6974 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6980 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp201 ISD::LoadExtType ExtType = LD->getExtensionType(); local
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
446 ISD::LoadExtType ExtType = LD->getExtensionType(); local
538 switch (ExtType) {
560 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
H A DLegalizeIntegerTypes.cpp446 ISD::LoadExtType ExtType = local
449 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
1859 ISD::LoadExtType ExtType = N->getExtensionType(); local
1872 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1878 if (ExtType == ISD::SEXTLOAD) {
1884 } else if (ExtType == ISD::ZEXTLOAD) {
1888 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1906 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1924 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1951 Hi = DAG.getNode(ExtType
[all...]
H A DLegalizeVectorTypes.cpp917 ISD::LoadExtType ExtType = LD->getExtensionType(); local
931 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
938 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
2232 ISD::LoadExtType ExtType = LD->getExtensionType(); local
2236 if (ExtType != ISD::NON_EXTLOAD)
2237 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2878 ISD::LoadExtType ExtType) {
2902 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2912 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2876 GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain, LoadSDNode *LD, ISD::LoadExtType ExtType) argument
H A DSelectionDAG.cpp236 ISD::NodeType ISD::getExtForLoadExtType(ISD::LoadExtType ExtType) { argument
237 switch (ExtType) {
2536 unsigned ExtType = LD->getExtensionType(); local
2537 switch (ExtType) {
4635 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument
4664 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
4668 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument
4673 ExtType = ISD::NON_EXTLOAD;
4674 } else if (ExtType == ISD::NON_EXTLOAD) {
4699 ID.AddInteger(encodeMemSDNodeFlags(ExtType, A
4737 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo) argument
4749 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) argument
[all...]
H A DDAGCombiner.cpp193 ISD::NodeType ExtType);
833 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) local
838 return DAG.getExtLoad(ExtType, dl, PVT,
1055 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) local
1059 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
4919 ISD::NodeType ExtType) {
4930 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5560 ISD::LoadExtType ExtType = LN0->getExtensionType(); local
5562 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, MemVT)) {
5563 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLo
4917 ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs, SDValue Trunc, SDValue ExtLoad, SDLoc DL, ISD::NodeType ExtType) argument
5668 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; local
9829 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, VecEltVT) local
[all...]
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1000 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); local
1006 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1010 ExtType == AArch64_AM::UXTX) ||
1012 ExtType == AArch64_AM::UXTW) ) {
1018 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
/external/llvm/include/llvm/Target/
H A DTargetLowering.h520 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { argument
521 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
523 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
527 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
529 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
1110 void setLoadExtAction(unsigned ExtType, MVT VT,
1112 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1114 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2829 unsigned ExtType = local
2832 if (ExtType == ISD::SEXTLOAD) {
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp1126 ISD::LoadExtType ExtType = Load->getExtensionType(); local
1130 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1134 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1141 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1148 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1184 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1203 if (ExtType == ISD::SEXTLOAD) {
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2038 ISD::LoadExtType ExtType = LD->getExtensionType(); local
2048 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2067 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2068 (ExtType == ISD::EXTLOAD))
2071 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));

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