Searched defs:Fixups (Results 1 - 25 of 26) sorted by relevance

12

/external/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.h32 SmallVectorImpl<MCFixup> &Fixups,
36 SmallVectorImpl<MCFixup> &Fixups,
35 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
H A DSIMCCodeEmitter.cpp58 SmallVectorImpl<MCFixup> &Fixups,
63 SmallVectorImpl<MCFixup> &Fixups,
130 SmallVectorImpl<MCFixup> &Fixups,
133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
174 SmallVectorImpl<MCFixup> &Fixups,
182 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
129 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
172 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
H A DR600MCCodeEmitter.cpp45 SmallVectorImpl<MCFixup> &Fixups,
50 SmallVectorImpl<MCFixup> &Fixups,
90 SmallVectorImpl<MCFixup> &Fixups,
100 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
124 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
134 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
89 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCFixupKinds.h19 enum Fixups { enum in namespace:llvm::PPC
H A DPPCMCCodeEmitter.cpp49 SmallVectorImpl<MCFixup> &Fixups,
52 SmallVectorImpl<MCFixup> &Fixups,
55 SmallVectorImpl<MCFixup> &Fixups,
58 SmallVectorImpl<MCFixup> &Fixups,
61 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
67 SmallVectorImpl<MCFixup> &Fixups,
70 SmallVectorImpl<MCFixup> &Fixups,
73 SmallVectorImpl<MCFixup> &Fixups,
76 SmallVectorImpl<MCFixup> &Fixups,
163 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
175 getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
188 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
201 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
213 getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
225 getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
244 getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
263 getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
279 getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
292 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
304 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86FixupKinds.h17 enum Fixups { enum in namespace:llvm::X86
H A DX86MCCodeEmitter.cpp125 SmallVectorImpl<MCFixup> &Fixups,
149 SmallVectorImpl<MCFixup> &Fixups,
153 SmallVectorImpl<MCFixup> &Fixups,
319 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
381 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
389 SmallVectorImpl<MCFixup> &Fixups,
422 CurByte, OS, Fixups, -ImmSize);
473 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
484 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
505 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
317 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const argument
385 EmitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1175 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64FixupKinds.h18 enum Fixups { enum in namespace:llvm::AArch64
H A DAArch64MCCodeEmitter.cpp50 SmallVectorImpl<MCFixup> &Fixups,
56 SmallVectorImpl<MCFixup> &Fixups,
64 SmallVectorImpl<MCFixup> &Fixups,
70 SmallVectorImpl<MCFixup> &Fixups,
76 SmallVectorImpl<MCFixup> &Fixups,
82 SmallVectorImpl<MCFixup> &Fixups,
88 SmallVectorImpl<MCFixup> &Fixups,
95 SmallVectorImpl<MCFixup> &Fixups,
101 SmallVectorImpl<MCFixup> &Fixups,
107 SmallVectorImpl<MCFixup> &Fixups,
216 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
227 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
248 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
274 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
301 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
323 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
343 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
352 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
371 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
393 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
421 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
445 getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
453 getSIMDShift64_32OpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
462 getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
471 getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
481 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
490 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
499 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
508 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
517 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
526 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
535 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
544 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
553 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
563 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
605 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUMCInstLower.cpp120 SmallVector<MCFixup, 4> Fixups; local
126 InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMFixupKinds.h17 enum Fixups { enum in namespace:llvm::ARM
H A DARMMCCodeEmitter.cpp69 SmallVectorImpl<MCFixup> &Fixups,
75 SmallVectorImpl<MCFixup> &Fixups,
82 SmallVectorImpl<MCFixup> &Fixups,
87 SmallVectorImpl<MCFixup> &Fixups,
93 SmallVectorImpl<MCFixup> &Fixups,
99 SmallVectorImpl<MCFixup> &Fixups,
104 SmallVectorImpl<MCFixup> &Fixups,
109 SmallVectorImpl<MCFixup> &Fixups,
114 SmallVectorImpl<MCFixup> &Fixups,
120 SmallVectorImpl<MCFixup> &Fixups,
191 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
264 getCCOutOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
273 getSOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
308 getT2SOImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
341 getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
509 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
567 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument
605 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
618 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
630 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
642 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
654 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
683 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
697 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
713 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
728 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
741 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
771 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
812 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
832 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
860 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
912 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
944 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
985 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
998 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1054 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1088 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1103 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1126 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1138 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1158 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1195 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1211 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1226 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1237 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1276 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1324 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp44 SmallVectorImpl<MCFixup> &Fixups,
50 SmallVectorImpl<MCFixup> &Fixups,
56 SmallVectorImpl<MCFixup> &Fixups,
60 SmallVectorImpl<MCFixup> &Fixups,
63 SmallVectorImpl<MCFixup> &Fixups,
66 SmallVectorImpl<MCFixup> &Fixups,
69 SmallVectorImpl<MCFixup> &Fixups,
84 SmallVectorImpl<MCFixup> &Fixups,
86 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
104 uint64_t op = getMachineOpValue(MI, MO, Fixups, ST
83 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
114 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
141 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
176 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
189 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
201 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
H A DSparcFixupKinds.h17 enum Fixups { enum in namespace:llvm::Sparc
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp39 SmallVectorImpl<MCFixup> &Fixups,
45 SmallVectorImpl<MCFixup> &Fixups,
49 // MO in MI. Fixups is the list of fixups against MI.
51 SmallVectorImpl<MCFixup> &Fixups,
59 SmallVectorImpl<MCFixup> &Fixups,
62 SmallVectorImpl<MCFixup> &Fixups,
65 SmallVectorImpl<MCFixup> &Fixups,
68 SmallVectorImpl<MCFixup> &Fixups,
71 SmallVectorImpl<MCFixup> &Fixups,
75 // Offset bytes from the start of MI. Add the fixup to Fixups
82 getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
87 getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
103 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
117 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
128 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
138 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
148 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
159 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
171 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
182 getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, unsigned Kind, int64_t Offset) const argument
[all...]
/external/llvm/lib/MC/
H A DMCMachOStreamer.cpp402 SmallVector<MCFixup, 4> Fixups; local
405 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
409 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
410 Fixups[i].setOffset(Fixups[i].getOffset() + DF->getContents().size());
411 DF->getFixups().push_back(Fixups[i]);
H A DWinCOFFStreamer.cpp49 SmallVector<MCFixup, 4> Fixups; local
52 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
56 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
57 Fixups[i].setOffset(Fixups[i].getOffset() + DF->getContents().size());
58 DF->getFixups().push_back(Fixups[i]);
H A DMCELFStreamer.cpp408 SmallVector<MCFixup, 4> Fixups; local
411 Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
414 for (unsigned i = 0, e = Fixups.size(); i != e; ++i)
415 fixSymbolsInTLSFixups(Fixups[i].getValue());
440 else if (!SD->isBundleLocked() && Fixups.size() == 0) {
466 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
467 Fixups[i].setOffset(Fixups[i].getOffset() + DF->getContents().size());
468 DF->getFixups().push_back(Fixups[i]);
H A DMCAssembler.cpp981 SmallVector<MCFixup, 4> Fixups; local
984 getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups, F.getSubtargetInfo());
990 F.getFixups() = Fixups;
1168 OS << " Fixups:[";
H A DMCAsmStreamer.cpp1177 SmallVector<MCFixup, 4> Fixups; local
1179 Emitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
1190 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
1191 MCFixup &F = Fixups[i];
1250 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
1251 MCFixup &F = Fixups[i];
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsFixupKinds.h25 enum Fixups { enum in namespace:llvm::Mips
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp54 SmallVectorImpl<MCFixup> &Fixups) const;
58 SmallVectorImpl<MCFixup> &Fixups) const;
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
66 SmallVectorImpl<MCFixup> &Fixups,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
151 SmallVectorImpl<MCFixup> &Fixups) const {
153 EmitTexInstr(MI, Fixups, OS);
164 uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
176 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
186 EmitALUInstr(MI, Fixups, O
192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
[all...]
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp54 SmallVectorImpl<MCFixup> &Fixups) const;
58 SmallVectorImpl<MCFixup> &Fixups) const;
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
66 SmallVectorImpl<MCFixup> &Fixups,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
151 SmallVectorImpl<MCFixup> &Fixups) const {
153 EmitTexInstr(MI, Fixups, OS);
164 uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
176 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
186 EmitALUInstr(MI, Fixups, O
192 EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
330 EmitALU(const MCInst &MI, unsigned numSrc, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
393 EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS) const argument
[all...]
/external/llvm/utils/TableGen/
H A DFixedLenDecoderEmitter.cpp608 static void resolveTableFixups(DecoderTable &Table, const FixupList &Fixups, argument
612 for (FixupList::const_reverse_iterator I = Fixups.rbegin(),
613 E = Fixups.rend();
/external/llvm/include/llvm/MC/
H A DMCAssembler.h215 /// Fixups - The list of fixups in this fragment.
216 SmallVector<MCFixup, 4> Fixups; member in class:llvm::MCDataFragment
230 return Fixups;
234 return Fixups;
243 fixup_iterator fixup_begin() override { return Fixups.begin(); }
244 const_fixup_iterator fixup_begin() const override { return Fixups.begin(); }
246 fixup_iterator fixup_end() override {return Fixups.end();}
247 const_fixup_iterator fixup_end() const override {return Fixups.end();}
304 /// Fixups - The list of fixups in this fragment.
305 SmallVector<MCFixup, 1> Fixups; member in class:llvm::MCRelaxableFragment
[all...]

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