/external/chromium_org/third_party/opus/src/silk/ |
H A D | decode_indices.c | 38 opus_int FrameIndex, /* I Frame number */ 51 if( decode_LBRR || psDec->VAD_flags[ FrameIndex ] ) { 35 silk_decode_indices( silk_decoder_state *psDec, ec_dec *psRangeDec, opus_int FrameIndex, opus_int decode_LBRR, opus_int condCoding ) argument
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H A D | encode_indices.c | 38 opus_int FrameIndex, /* I Frame number */ 50 psIndices = &psEncC->indices_LBRR[ FrameIndex ]; 35 silk_encode_indices( silk_encoder_state *psEncC, ec_enc *psRangeEnc, opus_int FrameIndex, opus_int encode_LBRR, opus_int condCoding ) argument
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H A D | dec_API.c | 271 opus_int FrameIndex; local 274 FrameIndex = channel_state[ 0 ].nFramesDecoded - n; 276 if( FrameIndex <= 0 ) { 279 condCoding = channel_state[ n ].LBRR_flags[ FrameIndex - 1 ] ? CODE_CONDITIONALLY : CODE_INDEPENDENTLY;
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/external/libopus/silk/ |
H A D | decode_indices.c | 38 opus_int FrameIndex, /* I Frame number */ 51 if( decode_LBRR || psDec->VAD_flags[ FrameIndex ] ) { 35 silk_decode_indices( silk_decoder_state *psDec, ec_dec *psRangeDec, opus_int FrameIndex, opus_int decode_LBRR, opus_int condCoding ) argument
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H A D | encode_indices.c | 38 opus_int FrameIndex, /* I Frame number */ 50 psIndices = &psEncC->indices_LBRR[ FrameIndex ]; 35 silk_encode_indices( silk_encoder_state *psEncC, ec_enc *psRangeEnc, opus_int FrameIndex, opus_int encode_LBRR, opus_int condCoding ) argument
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H A D | dec_API.c | 271 opus_int FrameIndex; local 274 FrameIndex = channel_state[ 0 ].nFramesDecoded - n; 276 if( FrameIndex <= 0 ) { 279 condCoding = channel_state[ n ].LBRR_flags[ FrameIndex - 1 ] ? CODE_CONDITIONALLY : CODE_INDEPENDENTLY;
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/external/llvm/lib/Target/R600/ |
H A D | SIMachineFunctionInfo.cpp | 87 void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex, argument 90 SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane); 94 SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) { argument 95 return SpilledRegisters[FrameIndex];
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H A D | AMDGPUInstrInfo.cpp | 48 int &FrameIndex) const { 54 int &FrameIndex) const { 61 int &FrameIndex) const { 66 int &FrameIndex) const { 71 int &FrameIndex) const { 77 int &FrameIndex) const { 109 int FrameIndex, 118 unsigned DestReg, int FrameIndex, 176 int FrameIndex) const { 106 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 116 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local 117 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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H A D | MSP430ISelDAGToDAG.cpp | 45 int FrameIndex; member in struct:__anon26028::MSP430ISelAddressMode::__anon26030 71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'; 201 case ISD::FrameIndex: 205 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 263 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, 404 case ISD::FrameIndex: {
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 98 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local 101 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 70 int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); local 72 int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {} 48 int FrameIndex; member in struct:llvm::RegScavenger::ScavengedInfo 136 if (I->FrameIndex == FI) 146 if (I->FrameIndex >= 0) 147 A.push_back(I->FrameIndex);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 126 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local 132 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16RegisterInfo.cpp | 81 unsigned OpNo, int FrameIndex, 106 if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) 80 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const argument
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H A D | MipsRegisterInfo.cpp | 228 // FrameIndex represent objects inside a abstract stack. 229 // We must replace FrameIndex with an stack/frame pointer 240 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local 242 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 244 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 248 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
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H A D | MipsSERegisterInfo.cpp | 106 unsigned OpNo, int FrameIndex, 123 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex); 134 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI) 105 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 159 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local 163 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 44 int &FrameIndex) const { 50 int &FrameIndex) const { 57 int &FrameIndex) const { 62 int &FrameIndex) const { 67 int &FrameIndex) const { 73 int &FrameIndex) const { 125 int FrameIndex, 134 unsigned DestReg, int FrameIndex, 144 int FrameIndex) const { 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 45 int FrameIndex; member in union:llvm::X86AddressMode::__anon26195 69 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); 131 MIB.addFrameIndex(AM.Base.FrameIndex); 145 /// reference has base register as the FrameIndex offset until it is resolved.
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H A D | X86RegisterInfo.cpp | 477 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local 483 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister()); 485 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); 492 // FrameIndex with base register with EBP. Add an offset to the offset. 500 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea(); 502 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 60 /// the destination along with the FrameIndex of the loaded stack slot. If 64 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ 72 FrameIndex = MI->getOperand(1).getIndex(); 81 /// the source reg along with the FrameIndex of the loaded stack slot. If 86 int &FrameIndex) const { 94 FrameIndex = MI->getOperand(1).getIndex(); 371 int FrameIndex, 381 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex), 383 MFI.getObjectSize(FrameIndex), 384 MFI.getObjectAlignment(FrameIndex)); 368 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 392 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | XCoreRegisterInfo.cpp | 266 int FrameIndex = FrameOp.getIndex(); local 273 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 281 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 44 int &FrameIndex) const { 50 int &FrameIndex) const { 57 int &FrameIndex) const { 62 int &FrameIndex) const { 67 int &FrameIndex) const { 73 int &FrameIndex) const { 125 int FrameIndex, 134 unsigned DestReg, int FrameIndex, 144 int FrameIndex) const { 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 627 int FrameIndex = getStackSpaceFor(VirtReg, RC); local 630 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
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