Searched defs:FrameIndex (Results 1 - 25 of 40) sorted by relevance

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/external/chromium_org/third_party/opus/src/silk/
H A Ddecode_indices.c38 opus_int FrameIndex, /* I Frame number */
51 if( decode_LBRR || psDec->VAD_flags[ FrameIndex ] ) {
35 silk_decode_indices( silk_decoder_state *psDec, ec_dec *psRangeDec, opus_int FrameIndex, opus_int decode_LBRR, opus_int condCoding ) argument
H A Dencode_indices.c38 opus_int FrameIndex, /* I Frame number */
50 psIndices = &psEncC->indices_LBRR[ FrameIndex ];
35 silk_encode_indices( silk_encoder_state *psEncC, ec_enc *psRangeEnc, opus_int FrameIndex, opus_int encode_LBRR, opus_int condCoding ) argument
H A Ddec_API.c271 opus_int FrameIndex; local
274 FrameIndex = channel_state[ 0 ].nFramesDecoded - n;
276 if( FrameIndex <= 0 ) {
279 condCoding = channel_state[ n ].LBRR_flags[ FrameIndex - 1 ] ? CODE_CONDITIONALLY : CODE_INDEPENDENTLY;
/external/libopus/silk/
H A Ddecode_indices.c38 opus_int FrameIndex, /* I Frame number */
51 if( decode_LBRR || psDec->VAD_flags[ FrameIndex ] ) {
35 silk_decode_indices( silk_decoder_state *psDec, ec_dec *psRangeDec, opus_int FrameIndex, opus_int decode_LBRR, opus_int condCoding ) argument
H A Dencode_indices.c38 opus_int FrameIndex, /* I Frame number */
50 psIndices = &psEncC->indices_LBRR[ FrameIndex ];
35 silk_encode_indices( silk_encoder_state *psEncC, ec_enc *psRangeEnc, opus_int FrameIndex, opus_int encode_LBRR, opus_int condCoding ) argument
H A Ddec_API.c271 opus_int FrameIndex; local
274 FrameIndex = channel_state[ 0 ].nFramesDecoded - n;
276 if( FrameIndex <= 0 ) {
279 condCoding = channel_state[ n ].LBRR_flags[ FrameIndex - 1 ] ? CODE_CONDITIONALLY : CODE_INDEPENDENTLY;
/external/llvm/lib/Target/R600/
H A DSIMachineFunctionInfo.cpp87 void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex, argument
90 SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
94 SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) { argument
95 return SpilledRegisters[FrameIndex];
H A DAMDGPUInstrInfo.cpp48 int &FrameIndex) const {
54 int &FrameIndex) const {
61 int &FrameIndex) const {
66 int &FrameIndex) const {
71 int &FrameIndex) const {
77 int &FrameIndex) const {
109 int FrameIndex,
118 unsigned DestReg, int FrameIndex,
176 int FrameIndex) const {
106 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
116 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local
117 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
H A DMSP430ISelDAGToDAG.cpp45 int FrameIndex; member in struct:__anon26028::MSP430ISelAddressMode::__anon26030
71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
201 case ISD::FrameIndex:
205 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
263 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex,
404 case ISD::FrameIndex: {
/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp98 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local
101 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
/external/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp70 int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); local
72 int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
/external/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(nullptr) {}
48 int FrameIndex; member in struct:llvm::RegScavenger::ScavengedInfo
136 if (I->FrameIndex == FI)
146 if (I->FrameIndex >= 0)
147 A.push_back(I->FrameIndex);
/external/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp126 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local
132 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
/external/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp81 unsigned OpNo, int FrameIndex,
106 if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
80 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const argument
H A DMipsRegisterInfo.cpp228 // FrameIndex represent objects inside a abstract stack.
229 // We must replace FrameIndex with an stack/frame pointer
240 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local
242 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
244 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
248 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
H A DMipsSERegisterInfo.cpp106 unsigned OpNo, int FrameIndex,
123 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
134 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
105 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp159 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local
163 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp44 int &FrameIndex) const {
50 int &FrameIndex) const {
57 int &FrameIndex) const {
62 int &FrameIndex) const {
67 int &FrameIndex) const {
73 int &FrameIndex) const {
125 int FrameIndex,
134 unsigned DestReg, int FrameIndex,
144 int FrameIndex) const {
122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h45 int FrameIndex; member in union:llvm::X86AddressMode::__anon26195
69 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
131 MIB.addFrameIndex(AM.Base.FrameIndex);
145 /// reference has base register as the FrameIndex offset until it is resolved.
H A DX86RegisterInfo.cpp477 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); local
483 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
485 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
492 // FrameIndex with base register with EBP. Add an offset to the offset.
500 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
502 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp60 /// the destination along with the FrameIndex of the loaded stack slot. If
64 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
72 FrameIndex = MI->getOperand(1).getIndex();
81 /// the source reg along with the FrameIndex of the loaded stack slot. If
86 int &FrameIndex) const {
94 FrameIndex = MI->getOperand(1).getIndex();
371 int FrameIndex,
381 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
383 MFI.getObjectSize(FrameIndex),
384 MFI.getObjectAlignment(FrameIndex));
368 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
392 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
H A DXCoreRegisterInfo.cpp266 int FrameIndex = FrameOp.getIndex(); local
273 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
281 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp44 int &FrameIndex) const {
50 int &FrameIndex) const {
57 int &FrameIndex) const {
62 int &FrameIndex) const {
67 int &FrameIndex) const {
73 int &FrameIndex) const {
125 int FrameIndex,
134 unsigned DestReg, int FrameIndex,
144 int FrameIndex) const {
122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/CodeGen/
H A DRegAllocFast.cpp627 int FrameIndex = getStackSpaceFor(VirtReg, RC); local
630 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);

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