Searched defs:GPR2AlignEncode (Results 1 - 6 of 6) sorted by relevance
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUCodeEmitter.h | 28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, function in class:llvm::AMDGPUCodeEmitter
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.h | 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, function in class:llvm::AMDGPUMCCodeEmitter
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| H A D | SIMCCodeEmitter.cpp | 86 /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
167 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI, function in class:SIMCCodeEmitter
209 | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUCodeEmitter.h | 28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, function in class:llvm::AMDGPUCodeEmitter
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.h | 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, function in class:llvm::AMDGPUMCCodeEmitter
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| H A D | SIMCCodeEmitter.cpp | 86 /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
167 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI, function in class:SIMCCodeEmitter
209 | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
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