Searched defs:Inst (Results 1 - 25 of 153) sorted by relevance

1234567

/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
H A DMCDisassembler.cpp19 bool MCDisassembler::tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, argument
25 return Symbolizer->tryAddingSymbolicOperand(Inst, cStream, Value, Address,
/external/clang/test/Parser/
H A Dcxx-default-args.cpp10 typedef struct Inst { struct
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_variable.h48 struct rc_instruction * Inst; member in struct:rc_variable
H A Dradeon_dataflow.h75 struct rc_instruction * Inst; member in struct:rc_reader
/external/llvm/include/llvm/MC/
H A DMCInstBuilder.h23 MCInst Inst; member in class:llvm::MCInstBuilder
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
62 return Inst;
/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
H A DMipsOs16.cpp65 const Instruction &Inst = *I; local
66 switch (Inst.getOpcode()) {
H A DMipsAnalyzeImmediate.cpp15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} function in class:MipsAnalyzeImmediate::Inst
18 void MipsAnalyzeImmediate::AddInstr(InstSeqLs &SeqLs, const Inst &I) {
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
45 AddInstr(SeqLs, Inst(SLL, Shamt));
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp51 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
57 Inst.addOperand(MCOperand::CreateReg(RegNo));
61 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
64 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs);
67 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
70 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs);
73 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
76 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
79 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
82 return decodeRegisterClass(Inst, RegN
[all...]
/external/llvm/lib/Transforms/ObjCARC/
H A DObjCARCExpand.cpp98 Instruction *Inst = &*I; local
100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n");
102 switch (GetBasicInstructionClass(Inst)) {
114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0);
115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n"
117 Inst->replaceAllUsesWith(Value);
H A DObjCARCAPElim.cpp99 Instruction *Inst = I++; local
100 switch (GetBasicInstructionClass(Inst)) {
102 Push = Inst;
107 if (Push && cast<CallInst>(Inst)->getArgOperand(0) == Push) {
111 " Pop: " << *Inst << "\n"
113 Inst->eraseFromParent();
119 if (MayAutorelease(ImmutableCallSite(Inst)))
H A DDependencyAnalysis.cpp36 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument
49 ImmutableCallSite CS = static_cast<const Value *>(Inst);
73 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument
81 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) {
87 } else if (ImmutableCallSite CS = static_cast<const Value *>(Inst)) {
96 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
106 for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end();
115 /// Test if there can be dependencies on Inst through Arg. This function only
118 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, argument
238 Instruction *Inst = --LocalStartPos; local
[all...]
/external/llvm/lib/Transforms/Scalar/
H A DDCE.cpp12 // Dead Inst Elimination performs a single pass over the function removing
48 Instruction *Inst = DI++; variable
49 if (isInstructionTriviallyDead(Inst, TLI)) {
50 Inst->eraseFromParent();
H A DLowerAtomic.cpp123 Instruction *Inst = DI++; variable
124 if (FenceInst *FI = dyn_cast<FenceInst>(Inst))
126 else if (AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(Inst))
128 else if (AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(Inst))
130 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
133 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_variable.h48 struct rc_instruction * Inst; member in struct:rc_variable
H A Dradeon_dataflow.h75 struct rc_instruction * Inst; member in struct:rc_reader
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp62 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( local
64 MAI->addInitialFrameState(Inst);
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp53 static void LowerLargeShift(MCInst& Inst) { argument
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst
[all...]
/external/llvm/lib/Analysis/
H A DDelinearization.cpp73 static Value *getPointerOperand(Instruction &Inst) { argument
74 if (LoadInst *Load = dyn_cast<LoadInst>(&Inst))
76 else if (StoreInst *Store = dyn_cast<StoreInst>(&Inst))
78 else if (GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(&Inst))
86 Instruction *Inst = &(*I); local
89 if (!isa<StoreInst>(Inst) && !isa<LoadInst>(Inst) &&
90 !isa<GetElementPtrInst>(Inst))
93 const BasicBlock *BB = Inst->getParent();
97 const SCEV *AccessFn = SE->getSCEVAtScope(getPointerOperand(*Inst),
113 O << "Inst:" << *Inst << "\\n"; local
[all...]
H A DLoads.cpp156 Instruction *Inst = --ScanFrom; local
157 if (isa<DbgInfoIntrinsic>(Inst))
170 if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
176 if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
205 if (Inst->mayWriteToMemory()) {
209 (AA->getModRefInfo(Inst, Ptr, AccessSize) & AliasAnalysis::Mod) == 0)
/external/llvm/lib/Object/
H A DRecordStreamer.cpp70 void RecordStreamer::EmitInstruction(const MCInst &Inst, argument
72 MCStreamer::EmitInstruction(Inst, STI);
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp172 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
175 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
179 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
182 return decodeRegisterClass(Inst, RegNo, CRRegs);
185 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
188 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
191 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
194 return decodeRegisterClass(Inst, RegNo, FRegs);
197 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
200 return decodeRegisterClass(Inst, RegN
[all...]
/external/llvm/tools/llvm-mc/
H A DDisassembler.cpp66 MCInst Inst; local
69 S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
92 Streamer.EmitInstruction(Inst, STI);
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
H A Dlp_bld_misc.cpp217 lp_set_load_alignment(LLVMValueRef Inst, argument
220 llvm::unwrap<llvm::LoadInst>(Inst)->setAlignment(Align);
225 lp_set_store_alignment(LLVMValueRef Inst, argument
228 llvm::unwrap<llvm::StoreInst>(Inst)->setAlignment(Align);

Completed in 358 milliseconds

1234567