/external/llvm/lib/Target/R600/ |
H A D | SIMachineFunctionInfo.cpp | 40 // VGPRs, we need to update the Lane VGPR's live interval every time we 53 // the Lane VGPR multiple times, this means any uses after the first aren't 56 // To work around this, we add Lane VGPRs to the functions live out list, 89 int Lane) { 90 SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane); 87 addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane) argument
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H A D | SIMachineFunctionInfo.h | 33 int Lane; member in struct:llvm::SIMachineFunctionInfo::SpilledReg 34 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } 35 SpilledReg() : VGPR(0), Lane(-1) { } 36 bool hasLane() { return Lane != -1;} 52 void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
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H A D | SIISelLowering.cpp | 1559 unsigned Lane = 0; local 1572 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used. 1573 // Note that subregs are packed, i.e. Lane==0 is the first bit set 1574 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit 1576 Lane = SubIdx2Lane(I->getConstantOperandVal(1)); 1580 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) { 1587 if (Users[Lane]) 1590 Users[Lane] = *I; 1610 SDLoc(), Users[Lane]->getValueType(0), 1612 DAG.ReplaceAllUsesWith(Users[Lane], Cop [all...] |
H A D | SIInstrInfo.cpp | 203 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF); local 208 .addImm(Lane); 209 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane); 335 .addImm(Spill.Lane + i); 358 .addImm(Spill.Lane + i);
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/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 67 unsigned Reg, unsigned Lane, 73 unsigned DReg, unsigned Lane, 88 DebugLoc DL, unsigned DReg, unsigned Lane, 428 unsigned Reg, unsigned Lane, bool QPR) { 437 .addImm(Lane)); 447 unsigned DReg, unsigned Lane, 454 .addReg(DReg, 0, Lane); 498 DebugLoc DL, unsigned DReg, unsigned Lane, 507 .addImm(Lane); 564 unsigned Lane; local 425 createDupLane(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg, unsigned Lane, bool QPR) argument 444 createExtractSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument 496 createInsertSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument [all...] |
H A D | ARMExpandPseudoInsts.cpp | 513 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); local 517 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 519 Lane -= RegElts; 521 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 566 MIB.addImm(Lane);
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H A D | ARMISelDAGToDAG.cpp | 2067 unsigned Lane = local 2143 Ops.push_back(getI32Imm(Lane));
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H A D | ARMBaseInstrInfo.cpp | 4004 unsigned SReg, unsigned &Lane) { 4006 Lane = 0; 4011 Lane = 1; 4026 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 4027 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 4035 unsigned DReg, unsigned Lane, 4046 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 4064 unsigned Lane; local 4103 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 4105 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 1 4003 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument 4033 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument [all...] |
H A D | ARMISelLowering.cpp | 5429 int Lane = SVN->getSplatIndex(); local 5431 if (Lane == -1) Lane = 0; 5434 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5440 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR && 5452 DAG.getConstant(Lane, MVT::i32)); 5562 SDValue Lane = Op.getOperand(2); local 5563 if (!isa<ConstantSDNode>(Lane)) 5571 SDValue Lane = Op.getOperand(1); local 5572 if (!isa<ConstantSDNode>(Lane)) 9445 SDValue Lane = N0.getOperand(1); local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 2878 unsigned Lane = MI->getOperand(2).getImm(); local 2880 if (Lane == 0) 2885 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); 2911 unsigned Lane = MI->getOperand(2).getImm() * 2; local 2914 if (Lane == 0) 2941 unsigned Lane = MI->getOperand(2).getImm(); local 2951 .addImm(Lane) 2975 unsigned Lane = MI->getOperand(2).getImm(); local 2985 .addImm(Lane)
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/external/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 3405 int Lane = cast<ConstantInt>(Ops[2])->getZExtValue(); local 3406 Value *SV = llvm::ConstantVector::get(ConstantInt::get(Int32Ty, 1-Lane)); 3414 Indices.push_back(ConstantInt::get(Int32Ty, 1-Lane)); 3415 Indices.push_back(ConstantInt::get(Int32Ty, Lane));
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/external/llvm/lib/Transforms/Vectorize/ |
H A D | SLPVectorizer.cpp | 543 Scalar(S), User(U), Lane(L){}; 549 int Lane; member in struct:__anon26372::BoUpSLP::ExternalUser 605 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { 606 Value *Scalar = Entry->Scalars[Lane]; 633 Lane << " from " << *Scalar << ".\n"); 634 ExternalUses.push_back(ExternalUser(Scalar, U, Lane)); 1399 I->Lane); 1561 for (unsigned Lane 1971 Value *Lane = Builder.getInt32(it->Lane); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 4613 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64); local 4614 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane); 4737 int Lane = SVN->getSplatIndex(); local 4739 if (Lane == -1) 4740 Lane = 0; 4742 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) 4748 !isa<ConstantSDNode>(V1.getOperand(Lane))) 4749 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane)); 4758 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue(); 4761 unsigned Idx = Lane > 5202 SDValue Lane = Op.getOperand(I); local 6724 SDValue Lane = Op1.getOperand(1); local [all...] |