Searched defs:Mask2 (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp728 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); local
729 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2,
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1091 unsigned Mask2 = RegInfo.createVirtualRegister(RC); local
1155 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1198 .addReg(OldVal).addReg(Mask2);
1324 unsigned Mask2 = RegInfo.createVirtualRegister(RC); local
1395 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1423 .addReg(OldVal).addReg(Mask2);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3254 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3267 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3272 SmallVector<int,4> Mask2; local
3281 Mask2.push_back(M0);
3293 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3301 if (TLI.isShuffleMaskLegal(Mask2, VT))
3303 N0->getOperand(0), &Mask2[0]);
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3867 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); local
3871 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3880 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
8297 unsigned Mask2 = N11C->getZExtValue(); local
8299 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8302 (Mask == ~Mask2)) {
8309 unsigned amt = countTrailingZeros(Mask2);
8318 (~Mask == Mask2)) {
8322 (Mask2 == 0xffff || Mask2
8389 unsigned Mask2 = N11C->getZExtValue(); local
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