Searched defs:Op0 (Results 1 - 25 of 56) sorted by relevance

123

/external/llvm/include/llvm/IR/
H A DGetElementPtrTypeIterator.h102 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument
103 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin());
108 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
H A DPatternMatch.h1179 m_Intrinsic(const T0 &Op0) { argument
1180 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));
1185 m_Intrinsic(const T0 &Op0, const T1 &Op1) { argument
1186 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));
1191 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument
1192 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1197 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument
1198 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
1204 m_BSwap(const Opnd0 &Op0) { argument
1205 return m_Intrinsic<Intrinsic::bswap>(Op0);
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/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp804 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local
810 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
845 uint32_t Op0 = (Bits >> 14) & 0x3; local
853 if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
858 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp248 MachineOperand &Op0 = MI->getOperand(0); local
249 unsigned Reg0 = Op0.getReg();
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp202 SDValue Op0, Op1; local
206 if (!SelectADDRrr(Op, Op0, Op1))
207 SelectADDRri(Op, Op0, Op1);
211 OutOps.push_back(Op0);
/external/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp164 Value *Op0 = C->getOperand(0); local
165 if (isa<Instruction>(Op0) &&
166 cast<Instruction>(Op0)->getParent() == C->getParent())
H A DScalarizer.cpp74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument
76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name);
85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument
87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name);
96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument
98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name);
370 Scatterer Op0 = scatter(&I, I.getOperand(0)); local
372 assert(Op0.size() == NumElems && "Mismatched binary operation");
377 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem],
398 Scatterer Op0 local
404 Value *Op0 = SI.getOperand(0); local
465 Scatterer Op0 = scatter(&CI, CI.getOperand(0)); local
485 Scatterer Op0 = scatter(&BCI, BCI.getOperand(0)); local
537 Scatterer Op0 = scatter(&SVI, SVI.getOperand(0)); local
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/external/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp488 Value *Op0 = CI->getArgOperand(0); local
489 Type *IntPtr = DL.getIntPtrType(Op0->getType());
493 Ops[0] = Op0;
/external/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp2020 GenericValue Op0 = getOperandValue(CE->getOperand(0), SF); local
2025 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break;
2026 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break;
2027 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break;
2028 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break;
2029 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break;
2030 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break;
2031 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break;
2032 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break;
2033 case Instruction::SDiv: Dest.IntVal = Op0
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp290 SDValue Op0, Op1; local
294 if (!SelectAddr(Op, Op0, Op1))
299 OutOps.push_back(Op0);
/external/llvm/lib/IR/
H A DAutoUpgrade.cpp366 Value *Op0 = CI->getArgOperand(0); local
387 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
H A DVerifier.cpp2260 Value *Op0 = MD->getOperand(0); local
2261 if (ConstantFP *CFP0 = dyn_cast_or_null<ConstantFP>(Op0)) {
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp92 unsigned Op0, bool Op0IsKill, uint64_t imm1,
266 Value *Op0 = I->getOperand(0); local
279 SrcReg = getRegForValue(Op0);
91 FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
33 if (isa<Constant>(Op0))
39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
314 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, argument
332 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this)) {
334 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n");
337 GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this));
342 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
348 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0))
355 if (SelectInst *SI = dyn_cast<SelectInst>(Op0))
[all...]
H A DInstCombineMulDivRem.cpp121 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
126 if (Value *V = SimplifyMulInst(Op0, Op1, DL))
133 return BinaryOperator::CreateNeg(Op0, I.getName());
174 if (Op0->hasOneUse()) {
177 if (match(Op0, m_Sub(m_Value(Y), m_Value(X))))
179 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1))))
193 if (SelectInst *SI = dyn_cast<SelectInst>(Op0))
197 if (isa<PHINode>(Op0))
205 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) {
215 if (Value *Op0v = dyn_castNegVal(Op0)) //
435 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
714 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
826 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument
836 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument
845 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument
867 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument
907 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
969 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1062 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1195 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1227 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1262 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
1336 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local
[all...]
/external/llvm/include/llvm/Analysis/
H A DScalarEvolution.h607 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
610 Ops.push_back(Op0);
625 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
628 Ops.push_back(Op0);
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp264 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); local
269 if (Op0 == X86::AX && Op1 == X86::AL)
273 if (Op0 == X86::EAX && Op1 == X86::AX)
277 if (Op0 == X86::RAX && Op1 == X86::EAX)
/external/llvm/lib/Analysis/
H A DConstantFolding.cpp612 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression.
616 static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, argument
626 unsigned BitWidth = DL->getTypeSizeInBits(Op0->getType()->getScalarType());
629 computeKnownBits(Op0, KnownZero0, KnownOne0, DL);
632 // All the bits of Op0 that the 'and' could be masking are already zero.
633 return Op0;
643 return ConstantInt::get(Op0->getType(), KnownOne);
653 if (IsConstantOffsetFromGlobal(Op0, GV1, Offs1, *DL))
656 unsigned OpSize = DL->getTypeSizeInBits(Op0->getType());
661 return ConstantInt::get(Op0
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H A DValueTracking.cpp48 static void computeKnownBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW, argument
53 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) {
83 llvm::computeKnownBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1);
131 static void computeKnownBitsMul(Value *Op0, Value *Op1, bool NSW, argument
137 computeKnownBits(Op0, KnownZero2, KnownOne2, TD, Depth+1);
143 if (Op0 == Op1) {
158 isKnownNonZero(Op0, TD, Depth)) ||
1350 Value *Op0 = I->getOperand(0); local
1356 // Turn Op0 << Op1 into Op0 *
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H A DInstructionSimplify.cpp137 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS))
138 if (Op0->getOpcode() == OpcodeToExpand) {
140 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS;
196 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS);
200 if (Op0 && Op0->getOpcode() == Opcode) {
201 Value *A = Op0->getOperand(0);
202 Value *B = Op0->getOperand(1);
242 if (Op0
520 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument
576 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
657 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument
770 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
779 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument
821 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument
857 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument
885 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
948 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
954 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
960 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
968 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
976 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1048 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1056 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1064 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1072 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1078 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument
1091 SimplifyFDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1099 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1153 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1161 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1169 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1177 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1183 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument
1196 SimplifyFRemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1231 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1269 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument
1285 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1294 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument
1316 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1326 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument
1352 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1362 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1448 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1456 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1569 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
1577 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument
1624 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument
[all...]
/external/llvm/lib/ExecutionEngine/
H A DExecutionEngine.cpp625 Constant *Op0 = CE->getOperand(0); local
629 GenericValue Result = getConstantValue(Op0);
638 GenericValue GV = getConstantValue(Op0);
644 GenericValue GV = getConstantValue(Op0);
650 GenericValue GV = getConstantValue(Op0);
657 GenericValue GV = getConstantValue(Op0);
663 GenericValue GV = getConstantValue(Op0);
668 GenericValue GV = getConstantValue(Op0);
683 GenericValue GV = getConstantValue(Op0);
699 GenericValue GV = getConstantValue(Op0);
[all...]
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp70 const MCOperand &Op0 = MI->getOperand(0); local
103 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
139 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
149 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
157 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
164 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 local
174 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
184 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp3589 SDValue Op0, Op1; local
3594 if (SelectDirectAddr(Op, Op0)) {
3595 OutOps.push_back(Op0);
3599 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
3600 OutOps.push_back(Op0);
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp286 // If Op0 is null, then Node is a constant that can be loaded using:
290 // If Op0 is nonnull, then Node can be implemented using:
292 // (Opcode (Opcode Op0 UpperVal) LowerVal)
293 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
399 SDValue Op0, uint64_t Op1) {
403 changeComponent(AM, IsBase, Op0);
422 SDValue Op0 = N.getOperand(0); local
425 unsigned Op0Code = Op0->getOpcode();
431 return expandAdjDynAlloc(AM, IsBase, Op0);
398 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument
936 SDValue Op0 = N->getOperand(I ^ 1); local
961 splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, uint64_t UpperVal, uint64_t LowerVal) argument
1093 SDValue Op0 = Node->getOperand(0); local
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp402 unsigned Op0 = getRegForValue(I->getOperand(0)); local
403 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
439 ISDOpcode, Op0, Op0IsKill, CF);
457 Op0, Op0IsKill,
893 unsigned Op0 = getRegForValue(I->getOperand(0)); local
894 if (Op0 == 0)
909 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
915 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1066 const Value *Op0 local
1284 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument
1352 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
1373 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
1397 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
1425 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1449 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument
1474 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument
1497 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1524 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument
1584 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument
1600 FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument
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