/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2, 76 SDValue Op1, SDValue Op2, 92 SDValue Op1, SDValue Op2, 106 SDValue Op1, SDValue Op2, 147 SDValue Op1, SDValue Op2, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 104 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 145 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 804 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local 806 Ops[1].getAsInteger(10, Op1); 810 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 846 uint32_t Op1 = (Bits >> 11) & 0x7; local 861 return "s3_" + utostr(Op1) + "_c" + utostr(CRn)
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 299 MachineOperand Op1 = MI->getOperand(S1); local 302 ChangeOpInto(MI->getOperand(S2), Op1);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 202 SDValue Op0, Op1; local 206 if (!SelectADDRrr(Op, Op0, Op1)) 207 SelectADDRri(Op, Op0, Op1); 212 OutOps.push_back(Op1);
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/external/llvm/lib/DebugInfo/ |
H A D | DWARFDebugFrame.cpp | 107 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK; local 112 addInstruction(Primary, Op1); 115 addInstruction(Primary, Op1, Data.getULEB128(Offset));
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/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 2021 GenericValue Op1 = getOperandValue(CE->getOperand(1), SF); local 2025 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break; 2026 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break; 2027 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break; 2028 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break; 2029 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break; 2030 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break; 2031 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break; 2032 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break; 2033 case Instruction::SDiv: Dest.IntVal = Op0.IntVal.sdiv(Op1 [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 290 SDValue Op0, Op1; local 294 if (!SelectAddr(Op, Op0, Op1)) 300 OutOps.push_back(Op1);
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/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 266 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 281 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 360 unsigned Op1, Op2; local 361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 365 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 373 unsigned Op1, Op2; local 374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 378 Inst.addOperand(MCOperand::CreateImm(Op1)); 386 unsigned Op1, Op2; local 399 unsigned Op1, Op2; local 413 unsigned Op1, Op2; local 426 unsigned Op1, Op2; local 439 unsigned Op1, Op2; local 524 unsigned Op1, Op2; local 538 unsigned Op1, Op2; local 552 unsigned Op1, Op2, Op3; local 565 unsigned Op1, Op2, Op3; local 578 unsigned Op1, Op2, Op3; local 591 unsigned Op1, Op2, Op3; local 604 unsigned Op1, Op2, Op3; local 618 unsigned Op1, Op2, Op3; local 633 unsigned Op1, Op2, Op3; local 647 unsigned Op1, Op2, Op3; local 661 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 695 unsigned Op1, Op2, Op3, Op4, Op5; local 715 unsigned Op1, Op2, Op3; local 734 unsigned Op1, Op2, Op3; local [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 34 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) 38 if (Constant *CUI = dyn_cast<Constant>(Op1)) 46 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { 50 Op1->getName()); 314 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, argument 319 if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(Op1)) 321 else if (ConstantVector *CV = dyn_cast<ConstantVector>(Op1)) 324 COp1 = dyn_cast<ConstantInt>(Op1); [all...] |
H A D | InstCombineMulDivRem.cpp | 121 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 126 if (Value *V = SimplifyMulInst(Op0, Op1, DL)) 132 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X 165 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { 191 if (isa<Constant>(Op1)) { 206 Value *Mul = Builder->CreateMul(C1, Op1); 210 return BinaryOperator::CreateAdd(Builder->CreateMul(X, Op1), Mul); 216 if (Value *Op1v = dyn_castNegVal(Op1)) 222 Value *Op1C = Op1; 228 BO = dyn_cast<BinaryOperator>(Op1); 435 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 714 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 826 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 836 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 845 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 867 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument 907 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 969 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1062 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1195 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1227 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1262 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1336 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | BuildLibCalls.cpp | 326 /// (e.g. 'fmin'). This function is known to take type matching 'Op1' and 'Op2' 327 /// and return one value with the same type. If 'Op1/Op2' are long double, 'l' 328 /// is added as the suffix of name, if 'Op1/Op2' is a float, we add a 'f' 330 Value *llvm::EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name, argument 333 AppendTypeSuffix(Op1, Name, NameBuffer); 336 Value *Callee = M->getOrInsertFunction(Name, Op1->getType(), 337 Op1->getType(), Op2->getType(), NULL); 338 CallInst *CI = B.CreateCall2(Callee, Op1, Op2, Name);
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/external/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 607 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 611 Ops.push_back(Op1); 625 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 629 Ops.push_back(Op1);
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/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 264 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); local 269 if (Op0 == X86::AX && Op1 == X86::AL) 273 if (Op0 == X86::EAX && Op1 == X86::AX) 277 if (Op0 == X86::RAX && Op1 == X86::EAX)
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 606 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument 611 Ops.push_back(Op1); 855 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); 856 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 858 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 860 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, 869 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1); 871 SDValue Op1, SDValue Op2); 873 SDValue Op1, SDValue Op2, SDValue Op3); 884 EVT VT2, SDValue Op1); [all...] |
/external/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 612 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression. 617 Constant *Op1, const DataLayout *DL){ 630 computeKnownBits(Op1, KnownZero1, KnownOne1, DL); 636 // All the bits of Op1 that the 'and' could be masking are already zero. 637 return Op1; 654 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *DL) && 1610 if (ConstantFP *Op1 = dyn_cast<ConstantFP>(Operands[0])) { 1613 double Op1V = getValueAsDouble(Op1); 1616 if (Op2->getType() != Op1->getType()) 1624 APFloat V1 = Op1 616 SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, Constant *Op1, const DataLayout *DL) argument [all...] |
H A D | ValueTracking.cpp | 48 static void computeKnownBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW, argument 62 llvm::computeKnownBits(Op1, KnownZero2, KnownOne2, TD, Depth+1); 86 llvm::computeKnownBits(Op1, KnownZero2, KnownOne2, TD, Depth+1); 131 static void computeKnownBitsMul(Value *Op0, Value *Op1, bool NSW, argument 136 computeKnownBits(Op1, KnownZero, KnownOne, TD, Depth+1); 143 if (Op0 == Op1) { 160 isKnownNonZero(Op1, TD, Depth)); 1351 Value *Op1 = I->getOperand(1); local 1354 ConstantInt *Op1CI = dyn_cast<ConstantInt>(Op1); 1356 // Turn Op0 << Op1 int [all...] |
H A D | InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) 161 if (Op1->getOpcode() == OpcodeToExpand) { 163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); 197 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); local 219 if (Op1 && Op1->getOpcode() == Opcode) { 221 Value *B = Op1->getOperand(0); 222 Value *C = Op1->getOperand(1); 261 if (Op1 520 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 576 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 657 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 770 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 779 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 821 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 857 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 885 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 948 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 954 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 960 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 968 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 976 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1048 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1056 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1064 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1072 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1078 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument 1091 SimplifyFDivInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1099 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1153 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1161 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1169 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1177 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1183 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument 1196 SimplifyFRemInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1231 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1269 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1285 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1294 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1316 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1326 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1352 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1362 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1448 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1456 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1569 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1577 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1624 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout *DL, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 671 SDValue Op1 = Op.getOperand(1); local 675 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 707 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 714 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); 716 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 848 SDValue Op1 = Op.getOperand(1); local 863 TLI.getBooleanContents(Op1.getValueType()) != 870 if (VT.getSizeInBits() != Op1 [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.cpp | 71 const MCOperand &Op1 = MI->getOperand(1); local 104 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg())); 140 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift; 149 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 157 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 164 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 675 const MCOperand &Op1 = MI->getOperand(0); local 680 unsigned Op1Val = Op1.getImm();
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 631 SDValue Op1 = N->getOperand(1); local 691 if (SelectDirectAddr(Op1, Addr)) { 744 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset) 745 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) { 798 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset) 799 : SelectADDRri(Op1.getNode(), Op1, Bas 1014 SDValue Op1; local 2000 SDValue Op1 = N->getOperand(1); local 3589 SDValue Op0, Op1; local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 397 // between the base and index. Try to fold Op1 into AM's displacement. 399 SDValue Op0, uint64_t Op1) { 401 int64_t TestDisp = AM.Disp + Op1; 423 SDValue Op1 = N.getOperand(1); local 426 unsigned Op1Code = Op1->getOpcode(); 429 return expandAdjDynAlloc(AM, IsBase, Op1); 434 return expandDisp(AM, IsBase, Op1, 438 cast<ConstantSDNode>(Op1)->getSExtValue()); 440 if (IsBase && expandIndex(AM, Op0, Op1)) 398 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument 1094 SDValue Op1 = Node->getOperand(1); local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 371 Scatterer Op1 = scatter(&I, I.getOperand(1)); local 373 assert(Op1.size() == NumElems && "Mismatched binary operation"); 377 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 390 Scatterer Op1 local 538 Scatterer Op1 = scatter(&SVI, SVI.getOperand(1)); local [all...] |
/external/llvm/include/llvm/IR/ |
H A D | PatternMatch.h | 1185 m_Intrinsic(const T0 &Op0, const T1 &Op1) { argument 1186 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1)); 1191 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument 1192 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2)); 1197 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1198 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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/external/llvm/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 1450 Constant *Op1 = nullptr; local 1455 Op1 = ValueList.getConstantFwdRef(Record[3], IdxTy); 1457 Op1 = ValueList.getConstantFwdRef(Record[2], Type::getInt32Ty(Context)); 1458 if (!Op1) 1460 V = ConstantExpr::getExtractElement(Op0, Op1); 1469 Constant *Op1 = ValueList.getConstantFwdRef(Record[1], local 1481 V = ConstantExpr::getInsertElement(Op0, Op1, Op2); 1489 Constant *Op1 = ValueList.getConstantFwdRef(Record[1], OpTy); local 1493 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2); 1503 Constant *Op1 local 1517 Constant *Op1 = ValueList.getConstantFwdRef(Record[2], OpTy); local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 602 unsigned Op1, Op2, NewDstIdx; local 603 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 605 if (Op1 == UseOpIdx) 608 NewDstIdx = Op1;
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