/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 14 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 17 const MCOperand &Op = MI->getOperand(OpNo); 29 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, argument 31 printOperand(MI, OpNo, O);
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/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 14 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 17 const MCOperand &Op = MI->getOperand(OpNo); 29 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, argument 31 printOperand(MI, OpNo, O);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument 47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument 51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 48 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 49 void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); 50 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, 53 void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { argument 54 printPostIncOperand(MI, OpNo, Amount, O); 57 void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 58 void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/external/llvm/lib/Target/Hexagon/InstPrinter/ |
H A D | HexagonInstPrinter.h | 37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const; 38 void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const; 39 void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const; 40 void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo, 42 void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 44 void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 46 void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 48 void printFrameIndexOperand(const MCInst *MI, unsigned OpNo, 50 void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) 52 void printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostrea 65 printSymbolHi(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 67 printSymbolLo(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument [all...] |
H A D | HexagonInstPrinter.cpp | 89 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 91 const MCOperand& MO = MI->getOperand(OpNo); 98 printImmOperand(MI, OpNo, O); 104 void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo, argument 106 const MCOperand& MO = MI->getOperand(OpNo); 111 O << MI->getOperand(OpNo).getImm(); 117 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo, argument 122 printOperand(MI, OpNo, O); 126 unsigned OpNo, raw_ostream &O) const { 127 O << MI->getOperand(OpNo) 125 printUnsignedImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 130 printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 135 printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 140 printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 149 printFrameIndexOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 157 printGlobalOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 164 printJumpTable(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 171 printConstantPool(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 178 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 185 printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 189 printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 193 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument 197 printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi) const argument [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 35 void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, argument 37 const MCOperand &Op = MI->getOperand(OpNo); 46 void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 49 const MCOperand &Op = MI->getOperand(OpNo); 60 void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, argument 63 const MCOperand &Base = MI->getOperand(OpNo); 64 const MCOperand &Disp = MI->getOperand(OpNo+1); 89 void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo, argument 91 unsigned CC = MI->getOperand(OpNo).getImm();
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument 40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument 47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument 51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
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/external/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.cpp | 73 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { argument 74 const MCOperand &Op = MI->getOperand(OpNo);
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/external/llvm/utils/TableGen/ |
H A D | AsmWriterInst.cpp | 171 unsigned OpNo = CGI.Operands.getOperandNamed(VarName); local 172 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo]; 176 OpNo, MIOp, Modifier));
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430AsmPrinter.cpp | 53 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 57 unsigned OpNo, unsigned AsmVariant, 127 bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, argument 134 printOperand(MI, OpNo, O); 139 unsigned OpNo, unsigned AsmVariant, 145 printSrcMemOperand(MI, OpNo, O); 138 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
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/external/llvm/lib/Transforms/Utils/ |
H A D | ValueMapper.cpp | 128 unsigned OpNo = 0, NumOperands = C->getNumOperands(); local 130 for (; OpNo != NumOperands; ++OpNo) { 131 Value *Op = C->getOperand(OpNo); 143 if (OpNo == NumOperands && NewTy == C->getType()) 150 for (unsigned j = 0; j != OpNo; ++j) 154 if (OpNo != NumOperands) { 158 for (++OpNo; OpNo != NumOperands; ++OpNo) [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveRangeCalc.cpp | 77 unsigned OpNo = (&MO - &MI->getOperand(0)); local 85 Idx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); 94 } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 110 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1; local 111 unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 299 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 301 const MCOperand &Op = MI->getOperand(OpNo);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 64 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, argument 66 const MachineOperand &MO = MI->getOperand(OpNo); 109 bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, argument 120 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, OS); 123 printOperand(MI, OpNo, OS); 127 if (!MI->getOperand(OpNo).isReg() || 128 OpNo+1 == MI->getNumOperands() || 129 !MI->getOperand(OpNo+1).isReg()) 131 ++OpNo; // Return the high-part. 136 if (MI->getOperand(OpNo) 146 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { argument 33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 34 return MI.getOperand(OpNo).getReg() == R; 188 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 190 const MCOperand &Op = MI->getOperand(OpNo); 256 unsigned OpNo, raw_ostream &OS) { 258 printOperand(&MI, OpNo, OS); 255 printAlias(const char *Str, const MCInst &MI, unsigned OpNo, raw_ostream &OS) argument
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16RegisterInfo.cpp | 81 unsigned OpNo, int FrameIndex, 114 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg()) 115 FrameReg = MI.getOperand(OpNo+2).getReg(); 132 Offset += MI.getOperand(OpNo + 1).getImm(); 149 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); 150 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); 80 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const argument
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H A D | MipsSERegisterInfo.cpp | 106 unsigned OpNo, int FrameIndex, 150 Offset += MI.getOperand(OpNo + 1).getImm(); 202 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); 203 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); 105 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const argument
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 82 void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 84 const MCOperand &Op = MI->getOperand(OpNo);
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 106 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, argument 109 unsigned Code = MI->getOperand(OpNo).getImm(); 200 printOperand(MI, OpNo+1, O); 203 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, argument 205 unsigned int Value = MI->getOperand(OpNo).getImm(); 210 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, argument 212 int Value = MI->getOperand(OpNo).getImm(); 217 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo, argument 219 unsigned int Value = MI->getOperand(OpNo).getImm(); 224 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo, argument 231 printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 239 printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 247 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 258 printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 267 printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 285 printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 296 printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 309 printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 337 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 48 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 51 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 54 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 57 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 60 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 63 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 66 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 69 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 72 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 75 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 163 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 175 getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 188 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 201 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 213 getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 225 getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 244 getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 263 getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 279 getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 292 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 44 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const; 77 unsigned OpNo) const { 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; 187 unsigned OpNo = 0; local 188 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) { 189 if (&MO == &MI.getOperand(OpNo)) 194 if (isSrcOperand(Desc, OpNo)) {
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 59 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 62 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 65 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, 68 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, 141 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, argument 144 const MCOperand &MO = MI.getOperand(OpNo); 176 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, argument 179 const MCOperand &MO = MI.getOperand(OpNo); 189 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, argument 192 const MCOperand &MO = MI.getOperand(OpNo); 201 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 194 unsigned OpNo, 199 if (!MI->getOperand(OpNo).isImm()) 201 OS << -int64_t(MI->getOperand(OpNo).getImm()); 204 MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo))); 211 unsigned OpNo, 215 SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(), 216 MI->getOperand(OpNo + 1).getImm(), 217 MI->getOperand(OpNo + 2).getReg(), OS); 193 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) argument 210 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) argument
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