Searched defs:Opcode (Results 1 - 25 of 199) sorted by relevance

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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { argument
20 switch (Opcode) {
53 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { argument
54 switch (Opcode) {
H A DPPCMCCodeEmitter.cpp96 unsigned Opcode = MI.getOpcode(); variable
97 const MCInstrDesc &Desc = MCII.get(Opcode);
98 if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument
24 switch (Opcode) {
H A DARMHazardRecognizer.cpp26 unsigned Opcode = MCID.getOpcode(); local
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
/external/llvm/include/llvm/MC/
H A DMCInstBuilder.h27 MCInstBuilder(unsigned Opcode) { argument
28 Inst.setOpcode(Opcode);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h74 void EmitInt8(unsigned Opcode) { argument
75 Ops.push_back(Opcode & 0xff);
79 void EmitInt16(unsigned Opcode) { argument
80 Ops.push_back((Opcode >> 8) & 0xff);
81 Ops.push_back(Opcode & 0xff);
85 void EmitBytes(const uint8_t *Opcode, size_t Size) { argument
86 Ops.insert(Ops.end(), Opcode, Opcode + Size);
/external/smack/src/org/xbill/DNS/
H A DOpcode.java11 public final class Opcode { class
30 private static Mnemonic opcodes = new Mnemonic("DNS Opcode",
46 Opcode() {} method in class:Opcode
48 /** Converts a numeric Opcode into a String */
54 /** Converts a String representation of an Opcode into its numeric value */
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp87 int Opcode = InstIn.getOpcode(); local
89 if (Opcode == Mips::DEXT)
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
184 Opcode = NewOpcode;
/external/chromium_org/third_party/WebKit/Source/core/xml/
H A DXPathPredicate.h69 enum Opcode { enum in class:blink::XPath::FINAL
72 NumericOp(Opcode, PassOwnPtrWillBeRawPtr<Expression> lhs, PassOwnPtrWillBeRawPtr<Expression> rhs);
78 Opcode m_opcode;
83 enum Opcode { OpcodeEqual, OpcodeNotEqual, OpcodeGreaterThan, OpcodeLessThan, OpcodeGreaterOrEqual, OpcodeLessOrEqual }; enum in class:blink::XPath::FINAL
84 EqTestOp(Opcode, PassOwnPtrWillBeRawPtr<Expression> lhs, PassOwnPtrWillBeRawPtr<Expression> rhs);
91 Opcode m_opcode;
96 enum Opcode { OP_And, OP_Or }; enum in class:blink::XPath::FINAL
97 LogicalOp(Opcode, PassOwnPtrWillBeRawPtr<Expression> lhs, PassOwnPtrWillBeRawPtr<Expression> rhs);
104 Opcode m_opcode;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp133 unsigned Opcode; local
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
/external/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyLogical.h24 enum Opcode { enum in class:clang::threadSafety::lexpr::LExpr
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
/external/lldb/include/lldb/Core/
H A DOpcode.h1 //===-- Opcode.h ------------------------------------------------*- C++ -*-===//
28 class Opcode class in namespace:lldb_private
42 Opcode () : m_type (eTypeInvalid) function in class:lldb_private::Opcode
46 Opcode (uint8_t inst) : m_type (eType8) function in class:lldb_private::Opcode
51 Opcode (uint16_t inst) : m_type (eType16) function in class:lldb_private::Opcode
56 Opcode (uint32_t inst) : m_type (eType32) function in class:lldb_private::Opcode
61 Opcode (uint64_t inst) : m_type (eType64) function in class:lldb_private::Opcode
66 Opcode (uint8_t *bytes, size_t length) function in class:lldb_private::Opcode
74 m_type = Opcode::eTypeInvalid;
76 Opcode
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp84 unsigned Opcode = MI->getOpcode(); local
85 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
95 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
H A DSystemZAsmPrinter.cpp29 // Return an RI instruction like MI with opcode Opcode, but with the
31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { argument
33 return MCInstBuilder(Opcode)
37 return MCInstBuilder(Opcode)
43 // Return an RI instruction like MI with opcode Opcode, but with the
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { argument
47 return MCInstBuilder(Opcode)
51 return MCInstBuilder(Opcode)
57 // Return an RI instruction like MI with opcode Opcode, but with the
59 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) { argument
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp133 unsigned Opcode; local
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_program_pair.h72 unsigned int Opcode:8; member in struct:rc_pair_sub_instruction
/external/chromium_org/third_party/mesa/src/src/mesa/main/
H A Datifragshader.h53 GLenum Opcode[2]; member in struct:atifs_instruction
62 GLenum Opcode; member in struct:atifs_setupinst
/external/chromium_org/third_party/mesa/src/src/mesa/program/
H A Dprog_instruction.c144 gl_inst_opcode Opcode; member in struct:instruction_info
152 * \note Opcode should equal array index!
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
273 ASSERT(opcode == InstInfo[opcode].Opcode);
274 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp78 unsigned Opcode = MI->getOpcode(); local
80 switch(Opcode) {
104 if (Opcode == ARM::t2HINT)
168 if (Opcode == ARM::t2STMDB_UPD)
197 if (Opcode == ARM::t2LDMIA_UPD)
274 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
279 NewMI.setOpcode(Opcode);
813 unsigned Opcode = MI->getOpcode();
816 if (Opcode
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsMCInstLower.cpp178 lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode, argument
180 OutMI.setOpcode(Opcode);
H A DMipsSERegisterInfo.cpp69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) { argument
70 switch (Opcode) {
89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) { argument
90 switch (Opcode) {
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp278 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, argument
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
333 unsigned Opcode = MI->getOpcode(); local
336 GetInstrType(Opcode, isFirst, isSingle, isCracked,
370 if (HasCTRSet && Opcode == PPC::BCTRL)
391 unsigned Opcode = MI->getOpcode(); local
394 GetInstrType(Opcode, isFirst, isSingle, isCracked,
399 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
/external/llvm/lib/Target/R600/
H A DR600EmitClauseMarkers.cpp273 unsigned Opcode = PushBeforeModifier ? local
275 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp175 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; local
176 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
184 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; local
185 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
/external/llvm/utils/TableGen/
H A DX86RecognizableInstr.h46 uint8_t Opcode; member in class:llvm::X86Disassembler::RecognizableInstr

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