Searched defs:RCI (Results 1 - 8 of 8) sorted by relevance

/external/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp80 RCInfo &RCI = RegClass[RC->getID()]; local
85 if (!RCI.Order)
86 RCI.Order.reset(new MCPhysReg[NumRegs]);
111 RCI.Order[N++] = PhysReg;
115 RCI.NumRegs = N + CSRAlias.size();
116 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
124 RCI.Order[N++] = PhysReg;
129 if (StressRA && RCI.NumRegs > StressRA)
130 RCI.NumRegs = StressRA;
134 if (Super != RC && getNumAllocatableRegs(Super) > RCI
[all...]
H A DAggressiveAntiDepBreaker.cpp118 const RegisterClassInfo &RCI,
124 RegClassInfo(RCI),
117 AggressiveAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector& CriticalPathRCs) argument
H A DCriticalAntiDepBreaker.cpp31 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : argument
36 RegClassInfo(RCI),
H A DPostRASchedulerList.cpp192 AliasAnalysis *AA, const RegisterClassInfo &RCI,
207 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
209 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr));
190 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
H A DRegisterPressure.cpp189 RCI = rci;
626 const RegisterClassInfo *RCI,
636 unsigned Limit = RCI->getRegPressureSetLimit(i);
768 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
834 unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
962 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
623 computeExcessPressureDelta(ArrayRef<unsigned> OldPressureVec, ArrayRef<unsigned> NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef<unsigned> LiveThruPressureVec) argument
H A DRegAllocGreedy.cpp113 RegisterClassInfo RCI; member in class:__anon25792::RAGreedy
1498 const RegisterClassInfo &RCI) {
1506 return RCI.getNumAllocatableRegs(ConstrainedRC);
1536 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1546 TRI, RCI)) {
2325 RCI.runOnMachineFunction(mf);
1495 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
/external/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h71 const RCInfo &RCI = RegClass[RC->getID()]; local
72 if (Tag != RCI.Tag)
74 return RCI;
/external/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp113 RegisterClassInfo RCI; member in class:__anon25928::AArch64A57FPLoadBalancing
302 RCI.runOnMachineFunction(F);
490 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));

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