Searched defs:Reads (Results 1 - 5 of 5) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h154 /// Reads - One of the operands read the virtual register. This does not
156 bool Reads; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
177 /// Reads - Read or a super-register is read.
178 bool Reads; member in struct:llvm::MachineOperandIteratorBase::PhysRegInfo
/external/llvm/utils/TableGen/
H A DCodeGenSchedule.h70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
133 IdxVec Reads; member in struct:llvm::CodeGenSchedClass
148 return ItinClassDef == IC && Writes == W && Reads == R;
360 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
373 const IdxVec &Reads) const;
418 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
H A DSubtargetEmitter.cpp883 IdxVec Reads = SCI->Reads; local
898 Reads.clear();
900 Writes, Reads);
911 Writes, Reads);
992 for (unsigned UseIdx = 0, EndIdx = Reads.size();
995 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
/external/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp274 SmallVector<unsigned, 8> Reads; local
300 Reads.push_back(Reg);
303 while (!Reads.empty())
304 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
H A DRegisterCoalescer.cpp973 bool Reads, Writes; local
974 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
978 if (DstInt && !Reads && SubIdx)
979 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
989 MO.setIsUndef(!Reads);

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