/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument 87 unsigned Group2 = GetGroup(Reg2);
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H A D | TargetInstrInfo.cpp | 138 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local 149 Reg0 = Reg2; 151 } else if (HasDef && Reg0 == Reg2 && 169 MI->getOperand(Idx1).setReg(Reg2);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { 119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 115 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AsmBackend.cpp | 415 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); variable 426 Reg2 = getXRegFromWReg(Reg2); 428 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 431 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 434 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 437 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 440 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 445 Reg2 = getDRegFromBReg(Reg2); [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 84 unsigned Reg1, unsigned Reg2); 464 unsigned Reg1, unsigned Reg2) { 472 .addReg(Reg2) 461 createRegSequence(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg1, unsigned Reg2) argument
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H A D | Thumb2SizeReduction.cpp | 645 unsigned Reg2 = MI->getOperand(2).getReg(); local 648 || !isARMLowRegister(Reg2)) 650 if (Reg0 != Reg2) { 678 unsigned Reg2 = MI->getOperand(2).getReg(); local 679 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
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H A D | ARMFastISel.cpp | 2782 unsigned Reg2 = 0; local 2784 Reg2 = getRegForValue(Src2Value); 2785 if (Reg2 == 0) return false; 2798 MIB.addReg(Reg2);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 631 unsigned Reg2 = CSI[idx + 1].getReg(); local 653 assert(AArch64::GPR64RegClass.contains(Reg2) && 661 assert(AArch64::FPR64RegClass.contains(Reg2) && 671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx() 682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)) 706 unsigned Reg2 = CSI[i + 1].getReg(); local 724 assert(AArch64::GPR64RegClass.contains(Reg2) && 731 assert(AArch64::FPR64RegClass.contains(Reg2) && 740 << TRI->getName(Reg2) << ") [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 732 unsigned Reg2) { 741 Reg1 = Reg2; 742 Reg2 = Temp; 746 I.addOperand(MCOperand::CreateReg(Reg2)); 751 unsigned Reg2, unsigned Reg3) { 755 I.addOperand(MCOperand::CreateReg(Reg2)); 761 unsigned Reg2, unsigned FPReg1, 765 Reg1 = Reg2; 766 Reg2 = temp; 769 EmitInstrRegReg(MovOpc, Reg2, FPReg 731 EmitInstrRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2) argument 750 EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument 760 EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument [all...] |
H A D | MipsISelLowering.cpp | 2268 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local 2269 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2728 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), local 2730 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
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/external/llvm/lib/MC/ |
H A D | MCDwarf.cpp | 1092 unsigned Reg2 = Instr.getRegister2(); local 1096 Streamer.AddComment(Twine("Reg2 ") + Twine(Reg2)); 1100 Streamer.EmitULEB128IntValue(Reg2);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 252 unsigned Reg2 = MI->getOperand(2).getReg(); local 275 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 279 .addReg(Reg2, getKillRegState(Reg2IsKill)) 286 MI->getOperand(0).setReg(Reg2); 290 MI->getOperand(1).setReg(Reg2);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1139 CodeGenRegister *Reg2 = i1->second; local 1141 if (Reg1 == Reg2) 1143 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); 1150 if (Reg2 == Reg3)
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5530 unsigned Reg2 = Op2.getReg(); local 5532 unsigned Rt2 = MRI->getEncodingValue(Reg2);
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