| /external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; member in class:llvm::RegisterClassInfo
71 const RCInfo &RCI = RegClass[RC->getID()];
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| H A D | RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
154 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { argument
157 return scavengeRegister(RegClass, MBBI, SPAdj);
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 79 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; local
80 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
81 (AMDGPU::SSrc_64RegClassID == RegClass) ||
82 (AMDGPU::VSrc_32RegClassID == RegClass) ||
83 (AMDGPU::VSrc_64RegClassID == RegClass);
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| /external/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ argument
98 assert(RegClass && "Cannot create register without RegClass!");
99 assert(RegClass->isAllocatable() &&
100 "Virtual register RegClass must be allocatable.");
105 VRegInfo[Reg].first = RegClass;
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| H A D | TargetInstrInfo.cpp | 48 short RegClass = MCID.OpInfo[OpNum].RegClass; local
50 return TRI->getPointerRegClass(MF, RegClass);
53 if (RegClass < 0)
57 return TRI->getRegClass(RegClass);
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| /external/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 60 /// RegClass - This specifies the register class enumeration of the operand
64 int16_t RegClass; member in class:llvm::MCOperandInfo
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| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 132 int RegClass = Desc.OpInfo[OpIdx].RegClass; local
133 if (RegClass == -1)
136 return TM.getRegisterInfo()->getRegClass(RegClass);
290 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32); local
294 N->getOperand(0), RegClass);
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| H A D | SIISelLowering.cpp | 1180 /// \brief Test if RegClass is one of the VSrc classes
1181 static bool isVSrc(unsigned RegClass) { argument
1182 return AMDGPU::VSrc_32RegClassID == RegClass ||
1183 AMDGPU::VSrc_64RegClassID == RegClass;
1186 /// \brief Test if RegClass is one of the SSrc classes
1187 static bool isSSrc(unsigned RegClass) { argument
1188 return AMDGPU::SSrc_32RegClassID == RegClass ||
1189 AMDGPU::SSrc_64RegClassID == RegClass;
1283 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1315 /// \brief Does "Op" fit into register class "RegClass"
1327 ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, unsigned RegClass, bool &ScalarSlotUsed) const argument
1402 unsigned RegClass = Desc->OpInfo[Op].RegClass; local
1439 unsigned RegClass = Desc->OpInfo[Op].RegClass; local
[all...] |
| H A D | SIInstrInfo.cpp | 563 int RegClass = Desc.OpInfo[i].RegClass; local
564 if (!RI.regClassCanUseImmediate(RegClass) &&
584 int RegClass = Desc.OpInfo[i].RegClass; local
585 if (RegClass != -1) {
590 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
739 Desc.OpInfo[OpNo].RegClass == -1)
742 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
762 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1329 const TargetRegisterClass *RegClass = local
1331 if (!MRI.constrainRegClass(Op, RegClass)) {
1334 unsigned NewOp = createResultReg(RegClass);
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| H A D | ScheduleDAGRRList.cpp | 280 unsigned &RegClass, unsigned &Cost,
293 RegClass = RC->getID();
302 RegClass = RC->getID();
310 RegClass = RC->getID();
315 RegClass = TLI->getRepRegClassFor(VT)->getID();
276 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
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| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1259 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; local
1260 if (!RegClass->Allocatable)
1263 const CodeGenRegister::Set &Regs = RegClass->getMembers();
1525 // Create a RegUnitSet for each RegClass that contains all units in the class
1530 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1535 // Compute a unique RegUnitSet for each RegClass.
1713 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1566 SDValue RegClass = local
1570 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1577 SDValue RegClass = local
1581 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1588 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); local
1591 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1598 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); local
1601 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1609 SDValue RegClass = local
1615 const SDValue Ops[] = { RegClass, V
1624 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); local
1638 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); local
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 177 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
1303 int16_t RegClassOp0 = Desc.OpInfo[0].RegClass;
1592 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { argument
1594 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1597 return getReg(RegClass, RegNum);
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