/external/vixl/src/a64/ |
H A D | assembler-a64.h | 38 typedef uint64_t RegList; typedef in namespace:vixl 39 static const int kRegListSizeInBits = sizeof(RegList) * 8; 81 RegList Bit() const { 82 VIXL_ASSERT(code_ < (sizeof(RegList) * 8)); 83 return IsValid() ? (static_cast<RegList>(1) << code_) : 0; 318 inline CPURegList(CPURegister::RegisterType type, unsigned size, RegList list) 388 inline RegList list() const { 393 inline void set_list(RegList new_list) { 450 RegList list_;
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/external/llvm/utils/TableGen/ |
H A D | CallingConvEmitter.cpp | 110 ListInit *RegList = Action->getValueAsListInit("RegList"); local 111 if (RegList->getSize() == 1) { 113 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; 115 O << IndentStr << "static const MCPhysReg RegList" << ++Counter 118 for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) { 120 O << getQualifiedName(RegList->getElementAsRecord(i)); 123 O << IndentStr << "if (unsigned Reg = State.AllocateReg(RegList" 124 << Counter << ", " << RegList->getSize() << ")) {\n"; 131 ListInit *RegList local [all...] |
/external/chromium_org/v8/src/ |
H A D | frames.h | 16 typedef uint64_t RegList; typedef in namespace:v8::internal 18 typedef uint32_t RegList; 22 int NumRegs(RegList list);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.h | 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; local 34 if (unsigned Reg = State.AllocateReg(RegList, 4)) 49 if (unsigned Reg = State.AllocateReg(RegList, 4)) 196 const uint16_t *RegList; local 201 RegList = SRegList; 205 RegList = DRegList; 209 RegList = QRegList; 218 State.AllocateRegBlock(RegList, NumRegs, PendingHAMembers.size());
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H A D | ARMBaseRegisterInfo.cpp | 61 const MCPhysReg *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) local 65 if (!MF) return RegList; 88 return RegList;
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H A D | ARMAsmPrinter.cpp | 1041 SmallVector<unsigned, 4> RegList; local 1066 RegList.push_back(MO.getReg()); 1074 RegList.push_back(SrcReg); 1078 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
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H A D | ARMBaseInstrInfo.cpp | 1936 SmallVector<MachineOperand, 4> RegList; local 1938 RegList.push_back(MI->getOperand(i)); 1950 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, 1974 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, 1990 for (int i = RegList.size() - 1; i >= 0; --i) 1991 MIB.addOperand(RegList[i]);
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMTargetStreamer.cpp | 53 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 284 static const MCPhysReg RegList[] = { local 287 static const unsigned NbRegs = array_lengthof(RegList); 329 unsigned Reg = State.AllocateReg(RegList, NbRegs);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 187 static const MCPhysReg RegList[] = { local 191 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 56 static const MCPhysReg RegList[] = { local 60 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 71 if (unsigned Reg = State.AllocateReg(RegList, 6))
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 1774 const SmallVectorImpl<unsigned> &RegList = getRegList(); local 1776 I = RegList.begin(), E = RegList.end(); I != E; ++I) 2596 assert (Regs.size() > 0 && "RegList contains no registers?"); 2834 const SmallVectorImpl<unsigned> &RegList = getRegList(); local 2836 I = RegList.begin(), E = RegList.end(); I != E; ) {
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