| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon26033
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| /external/valgrind/main/none/tests/mips64/ |
| H A D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator in enum:__anon33136
189 case SRL:
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| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| H A D | memcpy.S | 111 #define SRL dsrl define
147 #define SRL srl define
238 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
360 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 184 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, local
186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 95 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
|
| /external/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 931 enum BinaryOp { ADD, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
|
| /external/pcre/dist/sljit/ |
| H A D | sljitNativeSPARC_common.c | 154 #define SRL (OPC1(0x2) | OPC3(0x26)) macro
|
| H A D | sljitNativeMIPS_common.c | 167 #define SRL (HI(0) | LO(2)) macro
1398 FAIL_IF(push_inst(compiler, SRL | TA(EQUAL_FLAG) | DA(EQUAL_FLAG) | SH_IMM(23), EQUAL_FLAG));
1406 FAIL_IF(push_inst(compiler, SRL | TA(ULESS_FLAG) | DA(ULESS_FLAG) | SH_IMM(23), ULESS_FLAG));
1409 FAIL_IF(push_inst(compiler, SRL | TA(UGREATER_FLAG) | DA(UGREATER_FLAG) | SH_IMM(23), UGREATER_FLAG));
2096 FAIL_IF(push_inst(compiler, SRL | TA(sugg_dst_ar) | DA(sugg_dst_ar) | SH_IMM(23), sugg_dst_ar));
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 630 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1789 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1790 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1837 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1838 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1948 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1950 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1989 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1991 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2083 SDValue SRL local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 982 else if (Opc == ISD::SRL)
1222 case ISD::SRL: return visitSRL(N);
1308 case ISD::SRL:
2032 SDValue SRL = local
2033 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2036 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2037 AddToWorkList(SRL.getNode());
2086 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2100 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2244 N1 = DAG.getNode(ISD::SRL, D
[all...] |