Searched defs:STI (Results 1 - 25 of 104) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMFrameLowering.h24 const ARMSubtarget &STI; member in class:llvm::ARMFrameLowering
H A DARMBaseRegisterInfo.h85 const ARMSubtarget &STI; member in class:llvm::ARMBaseRegisterInfo
96 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
H A DThumb1InstrInfo.cpp23 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) argument
24 : ARMBaseInstrInfo(STI), RI(STI) {
H A DARMInstrInfo.cpp32 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) argument
33 : ARMBaseInstrInfo(STI), RI(STI) {
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h31 const AArch64Subtarget *STI; member in struct:llvm::AArch64RegisterInfo
/external/llvm/lib/Target/Mips/
H A DMipsFrameLowering.h25 const MipsSubtarget &STI; member in class:llvm::MipsFrameLowering
29 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
H A DMipsTargetStreamer.h145 const MCSubtargetInfo &STI; member in class:llvm::MipsTargetELFStreamer
151 MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
196 bool isO32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
197 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
198 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.h26 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument
27 : MCDisassembler(STI, Ctx) {}
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsELFStreamer.cpp15 const MCSubtargetInfo &STI, bool RelaxAll,
17 return new MipsELFStreamer(Context, MAB, OS, Emitter, STI);
13 createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
H A DMipsELFStreamer.h31 MCCodeEmitter *Emitter, const MCSubtargetInfo &STI)
39 const MCSubtargetInfo &STI, bool RelaxAll,
30 MipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI) argument
H A DMipsMCCodeEmitter.cpp38 const MCSubtargetInfo &STI,
45 const MCSubtargetInfo &STI,
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
125 const MCSubtargetInfo &STI,
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
147 const MCSubtargetInfo &STI) const
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
36 createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
43 createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
[all...]
/external/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.h25 const MCSubtargetInfo &STI; member in class:llvm::SparcInstPrinter
31 : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
/external/llvm/include/llvm/MC/
H A DMCDisassembler.h58 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument
59 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {}
90 const MCSubtargetInfo &STI; member in class:llvm::MCDisassembler
108 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
/external/llvm/lib/Target/NVPTX/
H A DNVPTXFrameLowering.cpp29 NVPTXFrameLowering::NVPTXFrameLowering(NVPTXSubtarget &STI) argument
31 is64bit(STI.is64Bit()) {}
/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp27 SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument
28 : MCDisassembler(STI, Ctx) {}
40 const MCSubtargetInfo &STI,
42 return new SystemZDisassembler(STI, Ctx);
323 return decodeInstruction(Table, MI, Inst, Address, this, STI);
39 createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h37 const TargetSubtargetInfo *STI; member in class:llvm::TargetSchedModel
44 TargetSchedModel(): STI(nullptr), TII(nullptr) {}
115 return STI->getWriteProcResBegin(SC);
118 return STI->getWriteProcResEnd(SC);
/external/llvm/lib/Object/
H A DRecordStreamer.cpp71 const MCSubtargetInfo &STI) {
72 MCStreamer::EmitInstruction(Inst, STI);
70 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp66 const MCSubtargetInfo &STI) {
61 createMSP430MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXMCTargetDesc.cpp66 const MCSubtargetInfo &STI) {
68 return new NVPTXInstPrinter(MAI, MII, MRI, STI);
61 createNVPTXMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp27 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument
28 : MCDisassembler(STI, Ctx) {}
42 const MCSubtargetInfo &STI,
44 return new PPCDisassembler(STI, Ctx);
346 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
41 createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/tools/llvm-mc/
H A DDisassembler.cpp57 const MCSubtargetInfo &STI) {
92 Streamer.EmitInstruction(Inst, STI);
159 MCSubtargetInfo &STI,
181 T.createMCDisassembler(STI, Ctx));
225 InAtomicBlock, STI);
53 PrintInsts(const MCDisassembler &DisAsm, const ByteArrayTy &Bytes, SourceMgr &SM, raw_ostream &Out, MCStreamer &Streamer, bool InAtomicBlock, const MCSubtargetInfo &STI) argument
157 disassemble(const Target &T, const std::string &Triple, MCSubtargetInfo &STI, MCStreamer &Streamer, MemoryBuffer &Buffer, SourceMgr &SM, raw_ostream &Out) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp69 const MCSubtargetInfo &STI) {
74 const MCSubtargetInfo &STI,
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
77 return createSIMCCodeEmitter(MCII, STI, Ctx);
79 return createR600MCCodeEmitter(MCII, STI, Ctx);
64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
73 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/CodeGen/
H A DLLVMTargetMachine.cpp171 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
178 MII, MRI, STI);
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
205 getTargetTriple(), *Context, *MAB, Out, MCE, STI, local
269 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
271 STI, *Ctx);
279 getTargetTriple(), *Ctx, *MAB, Out, MCE, STI, local
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp117 const MCSubtargetInfo &STI) {
119 return new AArch64InstPrinter(MAI, MII, MRI, STI);
121 return new AArch64AppleInstPrinter(MAI, MII, MRI, STI);
129 const MCSubtargetInfo &STI, bool RelaxAll,
112 createAArch64MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
126 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) argument
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp64 const MCSubtargetInfo &STI) :
67 setAvailableFeatures(STI.getFeatureBits());
61 ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument

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