Searched defs:ShOp (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp1064 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); local
1065 unsigned SBits = getShiftOp(ShOp);
1117 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); local
1119 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1584 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; local
1587 ShOp = ARM_AM::lsl;
1590 ShOp = ARM_AM::lsr;
1593 ShOp = ARM_AM::asr;
1596 ShOp = ARM_AM::ror;
1600 if (ShOp == ARM_AM::ror && imm == 0)
1601 ShOp = ARM_AM::rrx;
1609 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1611 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1889 SDValue ShOp = N->getOperand(1); local
1890 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
1896 SDValue ShOp = N->getOperand(1); local
1898 EVT ShVT = ShOp.getValueType();
1900 ShOp = GetWidenedVector(ShOp);
1901 ShVT = ShOp.getValueType();
1907 ShOp = ModifyToType(ShOp, ShWidenVT);
1909 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
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H A DDAGCombiner.cpp2542 SDValue ShOp = N0->getOperand(1); local
2546 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2548 ShOp = DAG.getConstant(0, VT);
2550 ShOp = SDValue();
2556 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2560 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2566 ShOp = N0->getOperand(0);
2567 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2569 ShOp = DAG.getConstant(0, VT);
2571 ShOp
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/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1697 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, argument
1700 Op->ShiftExtend.Type = ShOp;
2278 AArch64_AM::ShiftExtendType ShOp = local
2295 if (ShOp == AArch64_AM::InvalidShiftExtend)
2303 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR ||
2304 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR ||
2305 ShOp == AArch64_AM::MSL) {
2314 AArch64Operand::CreateShiftExtend(ShOp,
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