/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 161 MachineOperand &Src2 = MI->getOperand(2); local 165 unsigned SrcReg = Src2.getReg(); 178 MachineOperand &Src2 = MI->getOperand(2); local 179 if (Src2.getImm() != 32)
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/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 51 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \ 55 GenericValue Src2, Type *Ty) { 66 GenericValue Src2, Type *Ty) { 77 GenericValue Src2, Type *Ty) { 88 GenericValue Src2, Type *Ty) { 99 GenericValue Src2, Type *Ty) { 102 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); 105 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); 115 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \ 120 assert(Src1.AggregateVal.size() == Src2 54 executeFAddInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 65 executeFSubInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 76 executeFMulInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 87 executeFDivInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 98 executeFRemInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 137 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument 151 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument 165 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 156 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size), 159 SDValue Src1, SDValue Src2, uint64_t Size) { 171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, 174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, 193 SDValue Src1, SDValue Src2, SDValue Size, 199 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); 249 SDValue Src1, SDValue Src2, 253 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, 158 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument 192 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 248 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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H A D | SystemZISelLowering.cpp | 2226 SDValue Src2 = Node->getVal(); local 2233 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { 2235 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType()); 2259 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, 2263 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, 2268 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, 2293 SDValue Src2 local 2744 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3)); local 2867 unsigned Src2 = MI->getOperand(3).getReg(); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 308 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); local 312 .addOperand(Src2);
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H A D | X86InstrInfo.cpp | 1998 unsigned Src2 = MI->getOperand(2).getReg(); local 2002 if (Src == Src2) { 2017 .addReg(Src2, getKillRegState(isKill2)); 2021 LV->replaceKillInstruction(Src2, MI, InsMI2); 2249 const MachineOperand &Src2 = MI->getOperand(2); local 2253 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2270 if (LV && Src2.isKill()) 2280 unsigned Src2 = MI->getOperand(2).getReg(); local 2284 Src.getReg(), Src.isKill(), Src2, isKill2); 2293 LV->replaceKillInstruction(Src2, M [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, 139 Inst.addOperand(Src2); 131 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
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H A D | SparcISelLowering.cpp | 2681 SDValue Src2 = Op.getOperand(1); local 2682 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); 2683 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
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/external/llvm/lib/Target/R600/ |
H A D | SIInstrInfo.cpp | 665 const MachineOperand &Src2 = MI->getOperand(4); local 666 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { 668 !compareMachineOp(Src0, Src2)) {
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 7083 unsigned Src2 = MI->getOperand(2).getReg(); local 7097 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
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