/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 253 EVT SrcVT = Src.getValueType(); local 258 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 259 DAG.getConstant(Offset, SrcVT)),
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H A D | X86FastISel.cpp | 92 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 530 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 533 unsigned Src, EVT SrcVT, 535 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 1027 EVT SrcVT = TLI.getValueType(RV->getType()); local 1030 if (SrcVT != DstVT) { 1031 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) 1039 if (SrcVT 532 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 2086 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local 3149 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local [all...] |
H A D | X86ISelDAGToDAG.cpp | 503 MVT SrcVT = N->getOperand(0).getSimpleValueType(); local 507 if (SrcVT.isVector() || DstVT.isVector()) 514 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT); 535 MemVT = SrcIsSSE ? SrcVT : DstVT;
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H A D | X86ISelLowering.cpp | 5055 MVT SrcVT = SV->getSimpleValueType(0); local 5060 int NumElems = SrcVT.getVectorNumElements(); 5061 bool Is256BitVec = SrcVT.is256BitVector(); 5063 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) && 5078 MVT EltVT = SrcVT.getVectorElementType(); 5086 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 5239 EVT SrcVT = V.getValueType(); local 5242 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 10671 MVT SrcVT [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 1185 EVT SrcVT = Src.getValueType(); local 1192 if (SrcVT.bitsLE(MVT::i32)) { 1201 if (SrcVT.bitsLE(MVT::i64)) { 1205 } else if (SrcVT.bitsLE(MVT::i128)) { 1220 SrcVT = Src.getValueType(); 1228 switch (SrcVT.getSimpleVT().SimpleTy) { 1246 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, SrcVT),
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H A D | LegalizeVectorOps.cpp | 445 EVT SrcVT = LD->getMemoryVT(); local 450 unsigned NumElem = SrcVT.getVectorNumElements(); 452 EVT SrcEltVT = SrcVT.getScalarType(); 455 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { 471 unsigned RemainingBytes = SrcVT.getStoreSize(); 557 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; 563 SrcVT.getScalarType(), 747 EVT SrcVT = Src.getValueType(); local 748 int NumSrcElements = SrcVT.getVectorNumElements(); 762 DAG.getVectorShuffle(SrcVT, D 769 EVT SrcVT = Src.getValueType(); local 794 EVT SrcVT = Src.getValueType(); local [all...] |
H A D | FastISel.cpp | 839 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); local 842 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 852 if (!TLI.isTypeLegal(SrcVT)) 862 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 891 MVT SrcVT = SrcEVT.getSimpleVT(); 902 if (SrcVT == DstVT) { 903 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 915 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1186 EVT SrcVT local [all...] |
H A D | SelectionDAGISel.cpp | 638 EVT SrcVT = Src.getValueType(); local 639 if (!SrcVT.isInteger() || SrcVT.isVector())
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H A D | LegalizeIntegerTypes.cpp | 2796 EVT SrcVT = Op.getValueType(); local 2800 // The following optimization is valid only if every value in SrcVT (when 2802 // size of DstVT is >= than the number of bits in SrcVT -1. 2804 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 && 2805 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2819 if (SrcVT == MVT::i32) 2821 else if (SrcVT == MVT::i64) 2823 else if (SrcVT == MVT::i128) 2863 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
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H A D | LegalizeVectorTypes.cpp | 1010 EVT SrcVT = N->getOperand(0).getValueType(); local 1028 unsigned NumElements = SrcVT.getVectorNumElements(); 1030 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { 1034 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2), 1037 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2); 1040 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
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H A D | DAGCombiner.cpp | 10149 EVT SrcVT = MVT::Other; local 10173 if (SrcVT == MVT::Other) 10174 SrcVT = InVT; 10175 if (SrcVT != InVT) 10187 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 10189 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 10199 Opnds.push_back(DAG.getUNDEF(SrcVT));
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/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 478 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); local 479 if (!DstVT || !SrcVT) 483 unsigned SrcNumElems = SrcVT->getNumElements(); 515 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 129 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 786 MVT SrcVT; local 788 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) { 794 if (SrcVT == MVT::i64) 886 MVT SrcVT = SrcEVT.getSimpleVT(); 894 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 895 SrcVT == MVT::i8 || SrcVT 1224 MVT SrcVT = ArgVT; local 1234 MVT SrcVT = ArgVT; local 1750 EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 345 EVT SrcVT; local 347 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); 349 SrcVT = N.getOperand(0).getValueType(); 351 if (!IsLoadStore && SrcVT == MVT::i8) 353 else if (!IsLoadStore && SrcVT == MVT::i16) 355 else if (SrcVT == MVT::i32) 357 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); 362 EVT SrcVT = N.getOperand(0).getValueType(); local 363 if (!IsLoadStore && SrcVT == MVT::i8) 365 else if (!IsLoadStore && SrcVT [all...] |
H A D | AArch64ISelLowering.cpp | 2963 EVT SrcVT = In2.getValueType(); local 2964 if (SrcVT != VT) { 2965 if (SrcVT == MVT::f32 && VT == MVT::f64) 2967 else if (SrcVT == MVT::f64 && VT == MVT::f32) 5829 EVT SrcVT = LHS.getValueType(); local 5837 if (SrcVT.getVectorElementType().isFloatingPoint()) { 7197 MVT SrcVT = Src->getValueType(0).getSimpleVT(); local 7200 if (SrcVT.getSizeInBits() != 64) 7203 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits(); 7204 unsigned ElementCount = SrcVT 7682 EVT SrcVT = N0.getOperand(0).getValueType(); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 152 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 739 MVT SrcVT = SrcEVT.getSimpleVT(); 741 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) 754 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 755 SrcVT == MVT::i8 || SrcVT == MVT::i1) { 765 switch (SrcVT.SimpleTy) { 805 if (!PPCEmitIntExt(SrcVT, SrcReg 830 EVT SrcVT = TLI.getValueType(Src->getType(), true); local 848 EVT SrcVT = TLI.getValueType(Src->getType(), true); local 874 PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, bool IsSigned) argument 1025 MVT DstVT, SrcVT; local 1624 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument 1695 EVT SrcVT = TLI.getValueType(Src->getType(), true); local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 1030 EVT SrcVT = Src.getValueType(); local 1036 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { 1049 !SrcVT.isVector() || 1050 SrcVT.getVectorElementType() != MVT::i8) { 1058 unsigned NElts = SrcVT.getVectorNumElements(); 1059 if (!SrcVT.isSimple() && NElts != 3) 1065 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT); 1066 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
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H A D | AMDGPUISelLowering.cpp | 468 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { argument 475 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
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/external/llvm/lib/CodeGen/ |
H A D | CodeGenPrepare.cpp | 538 EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); local 542 if (SrcVT.isInteger() != DstVT.isInteger()) 547 if (SrcVT.bitsLT(DstVT)) return false; 552 if (TLI.getTypeAction(CI->getContext(), SrcVT) == 554 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); 560 if (SrcVT != DstVT)
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 1367 MVT SrcVT = SrcEVT.getSimpleVT(); 1381 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || 1382 SrcVT == MVT::i1) { 1396 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) 1404 switch (SrcVT.SimpleTy) { 1446 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg 2572 EVT SrcVT, DestVT; local 2590 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument [all...] |
H A D | ARMISelLowering.cpp | 3809 EVT SrcVT = Tmp1.getValueType(); local 3826 if (SrcVT == MVT::f32) { 3860 if (SrcVT == MVT::f64) 3952 EVT SrcVT = Op.getValueType(); local 3954 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3958 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3968 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3970 if (TLI.isBigEndian() && SrcVT.isVector() && 3971 SrcVT.getVectorNumElements() > 1) 3974 DAG.getNode(ARMISD::VREV64, dl, SrcVT, O [all...] |