| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | R600ISelLowering.h | 32 const R600InstrInfo * TII; member in class:llvm::R600TargetLowering
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| H A D | SIISelLowering.h | 24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
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| H A D | R600RegisterInfo.h | 28 const TargetInstrInfo &TII; member in struct:llvm::R600RegisterInfo
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| H A D | SIRegisterInfo.h | 28 const TargetInstrInfo &TII; member in struct:llvm::SIRegisterInfo
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| H A D | AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII = local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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| H A D | AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII; member in struct:llvm::AMDGPURegisterInfo
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | R600ISelLowering.h | 32 const R600InstrInfo * TII; member in class:llvm::R600TargetLowering
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| H A D | SIISelLowering.h | 24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
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| H A D | R600RegisterInfo.h | 28 const TargetInstrInfo &TII; member in struct:llvm::R600RegisterInfo
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| H A D | SIRegisterInfo.h | 28 const TargetInstrInfo &TII; member in struct:llvm::SIRegisterInfo
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| H A D | AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII = local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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| H A D | AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII; member in struct:llvm::AMDGPURegisterInfo
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 30 const AArch64InstrInfo *TII; member in struct:llvm::AArch64RegisterInfo
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| H A D | AArch64CleanupLocalDynamicTLSPass.cpp | 97 const AArch64InstrInfo *TII = TM->getInstrInfo(); local
102 TII->get(TargetOpcode::COPY),
117 const AArch64InstrInfo *TII = TM->getInstrInfo(); local
126 TII->get(TargetOpcode::COPY),
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineSSAUpdater.h | 54 const TargetInstrInfo *TII; member in class:llvm::MachineSSAUpdater
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| /external/llvm/lib/Target/R600/ |
| H A D | R600RegisterInfo.cpp | 30 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(ST.getInstrInfo()); local
52 TII->reserveIndirectRegisters(Reserved, MF);
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| H A D | SILowerI1Copies.cpp | 73 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( local
89 MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32));
95 MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
101 MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
119 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
131 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
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| H A D | SIRegisterInfo.cpp | 30 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); local
31 TII->reserveIndirectRegisters(Reserved, MF);
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| /external/llvm/lib/CodeGen/ |
| H A D | CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII; member in class:llvm::CriticalAntiDepBreaker
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| H A D | ErlangGC.cpp | 56 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); local
58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
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| H A D | DeadMachineInstructionElim.cpp | 35 const TargetInstrInfo *TII; member in class:__anon25737::DeadMachineInstructionElim
63 if (!MI->isSafeToMove(TII, nullptr, SawStore) && !MI->isPHI())
94 TII = MF.getTarget().getInstrInfo();
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameToArgsOffsetElim.cpp | 45 const XCoreInstrInfo &TII = local
56 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 33 const TargetInstrInfo *TII; member in class:llvm::InstrEmitter
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 49 const ARMBaseInstrInfo &TII = local
55 !(TII.getSubtarget().isLikeA9() &&
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
66 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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| H A D | Thumb2RegisterInfo.cpp | 43 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
49 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|