Searched defs:TII (Results 1 - 25 of 188) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ISelLowering.h32 const R600InstrInfo * TII; member in class:llvm::R600TargetLowering
H A DSIISelLowering.h24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
H A DR600RegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::R600RegisterInfo
H A DSIRegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::SIRegisterInfo
H A DAMDGPUConvertToISA.cpp49 const AMDGPUInstrInfo * TII = local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
H A DAMDGPURegisterInfo.h33 const TargetInstrInfo &TII; member in struct:llvm::AMDGPURegisterInfo
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ISelLowering.h32 const R600InstrInfo * TII; member in class:llvm::R600TargetLowering
H A DSIISelLowering.h24 const SIInstrInfo * TII; member in class:llvm::SITargetLowering
H A DR600RegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::R600RegisterInfo
H A DSIRegisterInfo.h28 const TargetInstrInfo &TII; member in struct:llvm::SIRegisterInfo
H A DAMDGPUConvertToISA.cpp49 const AMDGPUInstrInfo * TII = local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
H A DAMDGPURegisterInfo.h33 const TargetInstrInfo &TII; member in struct:llvm::AMDGPURegisterInfo
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h30 const AArch64InstrInfo *TII; member in struct:llvm::AArch64RegisterInfo
H A DAArch64CleanupLocalDynamicTLSPass.cpp97 const AArch64InstrInfo *TII = TM->getInstrInfo(); local
102 TII->get(TargetOpcode::COPY),
117 const AArch64InstrInfo *TII = TM->getInstrInfo(); local
126 TII->get(TargetOpcode::COPY),
/external/llvm/include/llvm/CodeGen/
H A DMachineSSAUpdater.h54 const TargetInstrInfo *TII; member in class:llvm::MachineSSAUpdater
/external/llvm/lib/Target/R600/
H A DR600RegisterInfo.cpp30 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(ST.getInstrInfo()); local
52 TII->reserveIndirectRegisters(Reserved, MF);
H A DSILowerI1Copies.cpp73 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( local
89 MI.setDesc(TII->get(AMDGPU::V_MOV_B32_e32));
95 MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
101 MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
119 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CNDMASK_B32_e64))
131 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64))
H A DSIRegisterInfo.cpp30 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); local
31 TII->reserveIndirectRegisters(Reserved, MF);
/external/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.h37 const TargetInstrInfo *TII; member in class:llvm::CriticalAntiDepBreaker
H A DErlangGC.cpp56 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); local
58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
H A DDeadMachineInstructionElim.cpp35 const TargetInstrInfo *TII; member in class:__anon25737::DeadMachineInstructionElim
63 if (!MI->isSafeToMove(TII, nullptr, SawStore) && !MI->isPHI())
94 TII = MF.getTarget().getInstrInfo();
/external/llvm/lib/Target/XCore/
H A DXCoreFrameToArgsOffsetElim.cpp45 const XCoreInstrInfo &TII = local
56 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h33 const TargetInstrInfo *TII; member in class:llvm::InstrEmitter
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp49 const ARMBaseInstrInfo &TII = local
55 !(TII.getSubtarget().isLikeA9() &&
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
66 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
H A DThumb2RegisterInfo.cpp43 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local
49 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))

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