Searched defs:VA (Results 1 - 25 of 26) sorted by relevance

12

/external/clang/test/Preprocessor/
H A Dmacro_paste_bad.c32 #define VA __VA_ ## ARGS__ macro
33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macro}} variable
/external/clang/test/Parser/
H A Dcxx-using-declaration.cpp4 int VA; member in namespace:A
9 using A::VA;
15 VA = 1;
/external/chromium_org/third_party/skia/src/sfnt/
H A DSkOTTable_OS_2.h31 struct VA : SkOTTableOS2_VA { } vA; struct in union:SkOTTableOS2::Version
45 SK_COMPILE_ASSERT(sizeof(SkOTTableOS2::Version::VA) == 68, sizeof_SkOTTableOS2__VA_not_68);
/external/skia/src/sfnt/
H A DSkOTTable_OS_2.h31 struct VA : SkOTTableOS2_VA { } vA; struct in union:SkOTTableOS2::Version
45 SK_COMPILE_ASSERT(sizeof(SkOTTableOS2::Version::VA) == 68, sizeof_SkOTTableOS2__VA_not_68);
/external/clang/test/CXX/special/class.dtor/
H A Dp3-0x.cpp140 struct VA { struct
142 virtual ~VA() {}
145 struct VB : VA
149 struct TVB : VA
/external/llvm/tools/llvm-readobj/
H A DARMWinEHPrinter.cpp187 Decoder::getSectionContaining(const COFFObjectFile &COFF, uint64_t VA) { argument
197 if (VA >= Address && (VA - Address) <= Size)
204 uint64_t VA, bool FunctionOnly) {
217 if (Address == VA)
523 uint64_t FunctionAddress, uint64_t VA) {
532 uint64_t Offset = VA - SectionVA;
203 getSymbol(const COFFObjectFile &COFF, uint64_t VA, bool FunctionOnly) argument
/external/mksh/src/
H A Dshf.c779 #define VA(type) va_arg(args, type) macro
828 tmp = VA(int);
889 lnum = (long)VA(ssize_t);
891 lnum = VA(long);
893 lnum = (long)(short)VA(int);
895 lnum = (long)VA(int);
902 lnum = VA(size_t);
904 lnum = VA(unsigned long);
906 lnum = (unsigned long)(unsigned short)VA(int);
908 lnum = (unsigned long)VA(unsigne
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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp876 Value *VA = PN.getIncomingValue(i); local
882 PN.setIncomingValue(j, VA);
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp451 CCValAssign &VA = ArgLocs[i]; local
452 if (VA.isRegLoc()) {
454 EVT RegVT = VA.getLocVT();
466 RegInfo.addLiveIn(VA.getLocReg(), VReg);
472 if (VA.getLocInfo() == CCValAssign::SExt)
474 DAG.getValueType(VA.getValVT()));
475 else if (VA.getLocInfo() == CCValAssign::ZExt)
477 DAG.getValueType(VA.getValVT()));
479 if (VA.getLocInfo() != CCValAssign::Full)
480 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA
547 CCValAssign &VA = RVLocs[i]; local
603 CCValAssign &VA = ArgLocs[i]; local
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/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1214 CCValAssign &VA = ArgLocs[i]; local
1215 unsigned Arg = ArgRegs[VA.getValNo()];
1216 MVT ArgVT = ArgVTs[VA.getValNo()];
1219 switch (VA.getLocInfo()) {
1223 MVT DestVT = VA.getLocVT();
1233 MVT DestVT = VA.getLocVT();
1245 if (VA.isRegLoc() && !VA.needsCustom()) {
1247 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1248 RegArgs.push_back(VA
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H A DAArch64ISelLowering.cpp1688 CCValAssign &VA = ArgLocs[i]; local
1700 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1707 if (VA.isRegLoc()) {
1709 EVT RegVT = VA.getLocVT();
1728 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1734 switch (VA.getLocInfo()) {
1740 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1753 } else { // VA.isRegLoc()
1754 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1755 unsigned ArgOffset = VA
1929 CCValAssign VA = RVLocs[i]; local
2247 CCValAssign &VA = ArgLocs[i]; local
2499 CCValAssign &VA = RVLocs[i]; local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp336 CCValAssign &VA = RVLocs[i]; local
338 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
342 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
448 CCValAssign &VA = ArgLocs[i]; local
449 if (VA.isMemLoc()) {
473 CCValAssign &VA = ArgLocs[i]; local
478 switch (VA.getLocInfo()) {
485 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
488 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA
861 CCValAssign &VA = ArgLocs[i]; local
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1213 CCValAssign &VA = ArgLocs[I]; local
1214 MVT ArgVT = ArgVTs[VA.getValNo()];
1219 !VA.isRegLoc() || VA.needsCustom())
1223 if (VA.getLocInfo() == CCValAssign::BCvt)
1250 CCValAssign &VA = ArgLocs[I]; local
1251 unsigned Arg = ArgRegs[VA.getValNo()];
1252 MVT ArgVT = ArgVTs[VA.getValNo()];
1255 switch (VA.getLocInfo()) {
1261 MVT DestVT = VA
1323 CCValAssign &VA = RVLocs[0]; local
1562 CCValAssign &VA = ValLocs[i]; local
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/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp1678 CCValAssign &VA = ArgLocs[i]; local
1683 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1705 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
H A DSIISelLowering.cpp397 CCValAssign &VA = ArgLocs[ArgIdx++]; local
398 EVT VT = VA.getLocVT();
400 if (VA.isMemLoc()) {
406 36 + VA.getLocMemOffset(),
411 assert(VA.isRegLoc() && "Parameter must be in a register!");
413 unsigned Reg = VA.getLocReg();
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1070 const CCValAssign &VA = RVLocs[i]; local
1071 if (VA.isRegLoc()) {
1072 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1077 assert(VA.isMemLoc());
1078 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
1148 CCValAssign &VA = ArgLocs[i]; local
1152 switch (VA.getLocInfo()) {
1156 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1159 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA
1313 CCValAssign &VA = ArgLocs[i]; local
1488 CCValAssign &VA = RVLocs[i]; local
1516 CCValAssign &VA = RVLocs[i]; local
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/external/chromium_org/third_party/libaddressinput/src/java/src/com/android/i18n/addressinput/
H A DRegionDataConstants.java1188 VA(new String[]{ enum constant in enum:RegionDataConstants.RegionDataEnum
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1893 CCValAssign &VA = ArgLocs[i]; local
1894 MVT ArgVT = ArgVTs[VA.getValNo()];
1901 if (VA.isRegLoc() && !VA.needsCustom()) {
1903 } else if (VA.needsCustom()) {
1905 if (VA.getLocVT() != MVT::f64 ||
1907 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1943 CCValAssign &VA = ArgLocs[i]; local
1944 unsigned Arg = ArgRegs[VA.getValNo()];
1945 MVT ArgVT = ArgVTs[VA
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H A DARMISelLowering.cpp1267 CCValAssign VA = RVLocs[i]; local
1272 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1279 if (VA.needsCustom()) {
1281 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1285 VA = RVLocs[++i]; // skip ahead to next loc
1286 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1294 if (VA.getLocVT() == MVT::v2f64) {
1299 VA = RVLocs[++i]; // skip ahead to next loc
1300 Lo = DAG.getCopyFromReg(Chain, dl, VA
1336 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
1349 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
1449 CCValAssign &VA = ArgLocs[i]; local
2002 CCValAssign &VA = ArgLocs[i]; local
2105 CCValAssign &VA = RVLocs[i]; local
2687 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, SDLoc dl) const argument
2946 CCValAssign &VA = ArgLocs[i]; local
2982 CCValAssign &VA = ArgLocs[i]; local
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/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp206 CCValAssign &VA = RVLocs[i]; local
207 assert(VA.isRegLoc() && "Can only return in registers!");
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
268 CCValAssign &VA = RVLocs[i]; local
269 assert(VA.isRegLoc() && "Can only return in registers!");
273 switch (VA.getLocInfo()) {
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA
360 CCValAssign &VA = ArgLocs[i]; local
560 CCValAssign &VA = ArgLocs[i]; local
747 CCValAssign &VA = ArgLocs[i]; local
1009 const CCValAssign &VA = ArgLocs[i]; local
1270 CCValAssign &VA = RVLocs[i]; local
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/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp1012 CCValAssign &VA = ValLocs[0];
1015 if (VA.getLocInfo() != CCValAssign::Full)
1018 if (!VA.isRegLoc())
1023 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
1026 unsigned SrcReg = Reg + VA.getValNo();
1028 EVT DstVT = VA.getValVT();
1052 unsigned DstReg = VA.getLocReg();
1061 RetRegs.push_back(VA.getLocReg());
2849 CCValAssign &VA local
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H A DX86ISelLowering.cpp1887 CCValAssign &VA = RVLocs[i]; local
1888 assert(VA.isRegLoc() && "Can only return in registers!");
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1895 else if (VA.getLocInfo() == CCValAssign::ZExt)
1896 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1897 else if (VA.getLocInfo() == CCValAssign::AExt)
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1899 else if (VA.getLocInfo() == CCValAssign::BCvt)
1900 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA
2051 CCValAssign &VA = RVLocs[i]; local
2187 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument
2266 CCValAssign &VA = ArgLocs[i]; local
2515 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
2686 CCValAssign &VA = ArgLocs[i]; local
2816 CCValAssign &VA = ArgLocs[i]; local
3235 CCValAssign &VA = RVLocs[i]; local
3297 CCValAssign &VA = ArgLocs[i]; local
3326 CCValAssign &VA = ArgLocs[i]; local
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/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2458 CCValAssign &VA = ArgLocs[i]; local
2459 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2476 switch (VA.getLocInfo()) {
2479 if (VA.isRegLoc()) {
2491 unsigned LocRegLo = VA.getLocReg();
2512 if (VA.isRegLoc()) {
2513 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2518 assert(VA.isMemLoc());
2522 MemOpChains.push_back(passArgOnStack(StackPtr, VA
2677 CCValAssign &VA = ArgLocs[i]; local
2829 CCValAssign &VA = RVLocs[i]; local
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/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp622 // Value is a value that has been passed to us in the location described by VA
623 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
626 CCValAssign &VA, SDValue Chain,
630 if (VA.getLocInfo() == CCValAssign::SExt)
631 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
632 DAG.getValueType(VA.getValVT()));
633 else if (VA.getLocInfo() == CCValAssign::ZExt)
634 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
635 DAG.getValueType(VA
625 convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Chain, SDValue Value) argument
650 convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, CCValAssign &VA, SDValue Value) argument
689 CCValAssign &VA = ArgLocs[I]; local
790 CCValAssign &VA = ArgLocs[I]; local
842 CCValAssign &VA = ArgLocs[I]; local
949 CCValAssign &VA = RetLocs[I]; local
988 CCValAssign &VA = RetLocs[I]; local
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/external/qemu/disas/
H A Dppc.c820 /* The VA field in a VA, VX or VXR form instruction. */
821 #define VA UI + 1
824 /* The VB field in a VA, VX or VXR form instruction. */
825 #define VB VA + 1
828 /* The VC field in a VA form instruction. */
832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
846 /* The SHB field in a VA form instruction. */
1723 /* An VA form instruction. */
1726 /* The mask for an VA for
817 #define VA macro
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