/external/chromium_org/third_party/libvpx/source/libvpx/vp9/encoder/x86/ |
H A D | vp9_subpel_variance_impl_intrin_avx2.c | 70 dst_reg = _mm256_loadu_si256((__m256i const *) (dst)); 85 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \ 86 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \ 129 __m256i src_reg, dst_reg, exp_src_lo, exp_src_hi, exp_dst_lo, exp_dst_hi; local 323 __m256i src_reg, dst_reg, exp_src_lo, exp_src_hi, exp_dst_lo, exp_dst_hi; local
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/external/libvpx/libvpx/vp9/encoder/x86/ |
H A D | vp9_subpel_variance_impl_intrin_avx2.c | 70 dst_reg = _mm256_load_si256((__m256i const *) (dst)); 85 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \ 86 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \ 129 __m256i src_reg, dst_reg, exp_src_lo, exp_src_hi, exp_dst_lo, exp_dst_hi; local 323 __m256i src_reg, dst_reg, exp_src_lo, exp_src_hi, exp_dst_lo, exp_dst_hi; local
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
H A D | i915_state_emit.c | 425 int dst_reg, 433 A0_DEST(dst_reg) | 444 int dst_reg = local 456 emit_instruction(i915, A0_MAD, A0_DEST_CHANNEL_ALL, t1_reg, dst_reg, cst0_reg, cst1_reg); 461 emit_instruction(i915, A0_EXP, dst_mask & A0_DEST_CHANNEL_X, dst_reg, t1x_reg, 0, 0); 462 emit_instruction(i915, A0_EXP, dst_mask & A0_DEST_CHANNEL_Y, dst_reg, t1y_reg, 0, 0); 463 emit_instruction(i915, A0_EXP, dst_mask & A0_DEST_CHANNEL_Z, dst_reg, t1z_reg, 0, 0); 422 emit_instruction(struct i915_context *i915, int op, int dst_mask, int dst_reg, int src0_reg, int src1_reg, int src2_reg) argument
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4.cpp | 107 src_reg::src_reg(dst_reg reg) 148 dst_reg::init() 155 dst_reg::dst_reg() function in class:brw::dst_reg 160 dst_reg::dst_reg(register_file file, int reg) function in class:brw::dst_reg 168 dst_reg::dst_reg(register_file file, int reg, const glsl_type *type, function in class:brw::dst_reg 179 dst_reg::dst_reg(struc function in class:brw::dst_reg 187 dst_reg::dst_reg(src_reg reg) function in class:brw::dst_reg [all...] |
H A D | brw_vec4.h | 42 class dst_reg; 108 explicit src_reg(dst_reg reg); 117 class dst_reg : public reg class in namespace:brw 134 dst_reg(); 135 dst_reg(register_file file, int reg); 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask); 137 dst_reg(struct brw_reg reg); 138 dst_reg(class vec4_visitor *v, const struct glsl_type *type); 140 explicit dst_reg(src_reg reg); 162 dst_reg ds [all...] |
H A D | brw_wm_fp.c | 134 static struct prog_dst_register dst_reg(GLuint file, GLuint idx) function 155 return dst_reg(PROGRAM_UNDEFINED, 0); 170 return dst_reg(PROGRAM_TEMPORARY, FIRST_INTERNAL_TEMP+(bit-1)); 370 struct prog_dst_register dst = dst_reg(PROGRAM_INPUT, idx);
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H A D | brw_fs_visitor.cpp | 1452 fs_reg dst_reg = reg; local 1461 dst_reg.type = src_reg.type; 1463 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1465 dst_reg.reg_offset++; 1476 dst_reg.type = src_reg.type; 1478 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1480 dst_reg.reg_offset++; 1489 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1492 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1495 emit(BRW_OPCODE_MOV, dst_reg, fs_re [all...] |
H A D | brw_vec4_visitor.cpp | 34 enum opcode opcode, dst_reg dst, 66 vec4_visitor::emit(enum opcode opcode, dst_reg dst, 75 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) 81 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0) 89 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst_reg())); 94 vec4_visitor::op(dst_reg dst, src_reg src0) \ 102 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \ 159 vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition) 183 vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index) 196 vec4_visitor::SCRATCH_WRITE(dst_reg ds 439 dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) function in class:brw::dst_reg [all...] |
/external/mesa3d/src/gallium/drivers/i915/ |
H A D | i915_state_emit.c | 425 int dst_reg, 433 A0_DEST(dst_reg) | 444 int dst_reg = local 456 emit_instruction(i915, A0_MAD, A0_DEST_CHANNEL_ALL, t1_reg, dst_reg, cst0_reg, cst1_reg); 461 emit_instruction(i915, A0_EXP, dst_mask & A0_DEST_CHANNEL_X, dst_reg, t1x_reg, 0, 0); 462 emit_instruction(i915, A0_EXP, dst_mask & A0_DEST_CHANNEL_Y, dst_reg, t1y_reg, 0, 0); 463 emit_instruction(i915, A0_EXP, dst_mask & A0_DEST_CHANNEL_Z, dst_reg, t1z_reg, 0, 0); 422 emit_instruction(struct i915_context *i915, int op, int dst_mask, int dst_reg, int src0_reg, int src1_reg, int src2_reg) argument
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vec4.cpp | 107 src_reg::src_reg(dst_reg reg) 148 dst_reg::init() 155 dst_reg::dst_reg() function in class:brw::dst_reg 160 dst_reg::dst_reg(register_file file, int reg) function in class:brw::dst_reg 168 dst_reg::dst_reg(register_file file, int reg, const glsl_type *type, function in class:brw::dst_reg 179 dst_reg::dst_reg(struc function in class:brw::dst_reg 187 dst_reg::dst_reg(src_reg reg) function in class:brw::dst_reg [all...] |
H A D | brw_vec4.h | 42 class dst_reg; 108 explicit src_reg(dst_reg reg); 117 class dst_reg : public reg class in namespace:brw 134 dst_reg(); 135 dst_reg(register_file file, int reg); 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask); 137 dst_reg(struct brw_reg reg); 138 dst_reg(class vec4_visitor *v, const struct glsl_type *type); 140 explicit dst_reg(src_reg reg); 162 dst_reg ds [all...] |
H A D | brw_wm_fp.c | 134 static struct prog_dst_register dst_reg(GLuint file, GLuint idx) function 155 return dst_reg(PROGRAM_UNDEFINED, 0); 170 return dst_reg(PROGRAM_TEMPORARY, FIRST_INTERNAL_TEMP+(bit-1)); 370 struct prog_dst_register dst = dst_reg(PROGRAM_INPUT, idx);
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H A D | brw_fs_visitor.cpp | 1452 fs_reg dst_reg = reg; local 1461 dst_reg.type = src_reg.type; 1463 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1465 dst_reg.reg_offset++; 1476 dst_reg.type = src_reg.type; 1478 emit(BRW_OPCODE_MOV, dst_reg, src_reg); 1480 dst_reg.reg_offset++; 1489 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); 1492 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); 1495 emit(BRW_OPCODE_MOV, dst_reg, fs_re [all...] |
H A D | brw_vec4_visitor.cpp | 34 enum opcode opcode, dst_reg dst, 66 vec4_visitor::emit(enum opcode opcode, dst_reg dst, 75 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) 81 vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0) 89 return emit(new(mem_ctx) vec4_instruction(this, opcode, dst_reg())); 94 vec4_visitor::op(dst_reg dst, src_reg src0) \ 102 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \ 159 vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition) 183 vec4_visitor::SCRATCH_READ(dst_reg dst, src_reg index) 196 vec4_visitor::SCRATCH_WRITE(dst_reg ds 439 dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) function in class:brw::dst_reg [all...] |
/external/chromium_org/third_party/mesa/src/chromium_gensrc/mesa/program/ |
H A D | program_parse.tab.h | 269 struct prog_dst_register dst_reg; member in union:YYSTYPE
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H A D | program_parse.tab.c | 454 struct prog_dst_register dst_reg; member in union:YYSTYPE 2386 (yyval.inst) = asm_instruction_ctor(OPCODE_ARL, & (yyvsp[(2) - (4)].dst_reg), & (yyvsp[(4) - (4)].src_reg), NULL, NULL); 2397 (yyval.inst) = asm_instruction_copy_ctor(& (yyvsp[(1) - (4)].temp_inst), & (yyvsp[(2) - (4)].dst_reg), & (yyvsp[(4) - (4)].src_reg), NULL, NULL); 2406 (yyval.inst) = asm_instruction_copy_ctor(& (yyvsp[(1) - (4)].temp_inst), & (yyvsp[(2) - (4)].dst_reg), & (yyvsp[(4) - (4)].src_reg), NULL, NULL); 2415 (yyval.inst) = asm_instruction_copy_ctor(& (yyvsp[(1) - (6)].temp_inst), & (yyvsp[(2) - (6)].dst_reg), & (yyvsp[(4) - (6)].src_reg), & (yyvsp[(6) - (6)].src_reg), NULL); 2424 (yyval.inst) = asm_instruction_copy_ctor(& (yyvsp[(1) - (6)].temp_inst), & (yyvsp[(2) - (6)].dst_reg), & (yyvsp[(4) - (6)].src_reg), & (yyvsp[(6) - (6)].src_reg), NULL); 2433 (yyval.inst) = asm_instruction_copy_ctor(& (yyvsp[(1) - (8)].temp_inst), & (yyvsp[(2) - (8)].dst_reg), & (yyvsp[(4) - (8)].src_reg), & (yyvsp[(6) - (8)].src_reg), & (yyvsp[(8) - (8)].src_reg)); 2442 (yyval.inst) = asm_instruction_copy_ctor(& (yyvsp[(1) - (8)].temp_inst), & (yyvsp[(2) - (8)].dst_reg), & (yyvsp[(4) - (8)].src_reg), NULL, NULL); 2500 (yyval.inst)->Base.DstReg.CondMask = (yyvsp[(2) - (2)].dst_reg).CondMask; 2501 (yyval.inst)->Base.DstReg.CondSwizzle = (yyvsp[(2) - (2)].dst_reg) [all...] |
/external/chromium_org/v8/src/arm/ |
H A D | macro-assembler-arm.h | 703 int dst_reg = (instr & dst_mask) >> dst_reg_offset; local 710 (dst_reg == src_reg) && 711 (FIRST_IC_MARKER <= dst_reg) && (dst_reg < LAST_CODE_MARKER)
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
H A D | r600_shader.c | 985 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg) argument 1002 alu.dst.sel = dst_reg; 1009 ar_reg = dst_reg; 1018 vtx.dst_gpr = dst_reg;
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/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
H A D | ir_to_mesa.cpp | 62 class dst_reg; 93 explicit src_reg(dst_reg reg); 103 class dst_reg { class 105 dst_reg(gl_register_file file, int writemask) function in class:dst_reg 114 dst_reg() function in class:dst_reg 123 explicit dst_reg(src_reg reg); 133 src_reg::src_reg(dst_reg reg) 142 dst_reg::dst_reg(src_reg reg) function in class:dst_reg 166 dst_reg ds [all...] |
/external/mesa3d/src/gallium/drivers/r600/ |
H A D | r600_shader.c | 985 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg) argument 1002 alu.dst.sel = dst_reg; 1009 ar_reg = dst_reg; 1018 vtx.dst_gpr = dst_reg;
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/external/mesa3d/src/mesa/program/ |
H A D | ir_to_mesa.cpp | 62 class dst_reg; 93 explicit src_reg(dst_reg reg); 103 class dst_reg { class 105 dst_reg(gl_register_file file, int writemask) function in class:dst_reg 114 dst_reg() function in class:dst_reg 123 explicit dst_reg(src_reg reg); 133 src_reg::src_reg(dst_reg reg) 142 dst_reg::dst_reg(src_reg reg) function in class:dst_reg 166 dst_reg ds [all...] |