| /external/chromium_org/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 1070 unsigned fbits) {
1072 scvtf(fd, rn, fbits);
1174 unsigned fbits) {
1176 ucvtf(fd, rn, fbits);
1068 Scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
1172 Ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
|
| H A D | assembler-arm64.cc | 2046 unsigned fbits) {
2047 if (fbits == 0) {
2050 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2058 unsigned fbits) {
2059 if (fbits == 0) {
2062 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2044 scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
2056 ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
|
| H A D | simulator-arm64.cc | 2302 int fbits = 64 - instr->FPScale(); local
2310 set_dreg(dst, FixedToDouble(xreg(src), fbits, round));
2313 set_dreg(dst, FixedToDouble(wreg(src), fbits, round));
2316 set_dreg(dst, UFixedToDouble(xreg(src), fbits, round));
2320 UFixedToDouble(reg<uint32_t>(src), fbits, round));
2324 set_sreg(dst, FixedToFloat(xreg(src), fbits, round));
2327 set_sreg(dst, FixedToFloat(wreg(src), fbits, round));
2330 set_sreg(dst, UFixedToFloat(xreg(src), fbits, round));
2334 UFixedToFloat(reg<uint32_t>(src), fbits, round));
2668 double Simulator::FixedToDouble(int64_t src, int fbits, FPRoundin argument
2678 UFixedToDouble(uint64_t src, int fbits, FPRounding round) argument
2694 FixedToFloat(int64_t src, int fbits, FPRounding round) argument
2704 UFixedToFloat(uint64_t src, int fbits, FPRounding round) argument
[all...] |
| /external/vixl/src/a64/ |
| H A D | simulator-a64.cc | 1439 int fbits = 64 - instr->FPScale(); local
1447 set_dreg(dst, FixedToDouble(xreg(src), fbits, round));
1450 set_dreg(dst, FixedToDouble(wreg(src), fbits, round));
1453 set_dreg(dst, UFixedToDouble(xreg(src), fbits, round));
1457 UFixedToDouble(static_cast<uint32_t>(wreg(src)), fbits, round));
1461 set_sreg(dst, FixedToFloat(xreg(src), fbits, round));
1464 set_sreg(dst, FixedToFloat(wreg(src), fbits, round));
1467 set_sreg(dst, UFixedToFloat(xreg(src), fbits, round));
1471 UFixedToFloat(static_cast<uint32_t>(wreg(src)), fbits, round));
1802 double Simulator::FixedToDouble(int64_t src, int fbits, FPRoundin argument
1812 UFixedToDouble(uint64_t src, int fbits, FPRounding round) argument
1828 FixedToFloat(int64_t src, int fbits, FPRounding round) argument
1838 UFixedToFloat(uint64_t src, int fbits, FPRounding round) argument
[all...] |
| H A D | assembler-a64.cc | 1488 unsigned fbits) {
1489 if (fbits == 0) {
1492 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
1500 unsigned fbits) {
1501 if (fbits == 0) {
1504 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
1486 scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
1498 ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
|