| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_build_util.h | 182 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; member in class:nv50_ir::BuildUtil
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_build_util.h | 182 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; member in class:nv50_ir::BuildUtil
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| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/translate/ |
| H A D | translate_sse.c | 455 unsigned imms[2] = {0, 0x3f800000}; local
658 x86_mov_imm(p->func, dst, imms[swizzle[0] - UTIL_FORMAT_SWIZZLE_0]);
668 x86_mov_imm(p->func, x86_make_disp(dst, 4), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]);
686 x86_mov_imm(p->func, x86_make_disp(dst, 8), imms[swizzle[2] - UTIL_FORMAT_SWIZZLE_0]);
696 x86_mov_imm(p->func, x86_make_disp(dst, 12), imms[swizzle[3] - UTIL_FORMAT_SWIZZLE_0]);
714 unsigned imms[2] = {0, 1}; local
773 imms[1] = (output_desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) ? 0xffff : 0x7ffff;
797 x86_mov16_imm(p->func, x86_make_disp(dst, 2), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]);
803 x86_mov_imm(p->func, dst, (imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0] << 16) | imms[swizzl
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| H A D | assembler-arm64-inl.h | 1067 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) { argument
1068 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1069 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1071 return imms << ImmS_offset;
1084 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) { argument
1086 DCHECK(is_uint6(imms));
1087 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1089 return imms << ImmSetBits_offset;
|
| H A D | assembler-arm64.cc | 1280 unsigned imms) {
1285 ImmS(imms, rn.SizeInBits()) |
1293 unsigned imms) {
1298 ImmS(imms, rn.SizeInBits()) |
1306 unsigned imms) {
1311 ImmS(imms, rn.SizeInBits()) |
2544 // N imms immr size S R
2716 // imms size S
2724 // So we 'or' (-d << 1) with our computed s to form imms.
1277 bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
1290 sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
1303 ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| H A D | AArch64InstPrinter.cpp | 117 int64_t imms = Op3.getImm(); local
118 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
120 shift = 31 - imms;
121 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
122 ((imms + 1 == immr))) {
124 shift = 63 - imms;
125 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
128 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
131 } else if (Opcode == AArch64::SBFMWri && imms
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 212 /// the form N:immr:imms.
294 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
297 // Extract the N, imms, and immr fields.
300 unsigned imms = val & 0x3f; local
303 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
307 unsigned S = imms & (size - 1);
322 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
326 // Extract the N and imms field
328 unsigned imms = val & 0x3f; local
[all...] |
| /external/mesa3d/src/gallium/auxiliary/translate/ |
| H A D | translate_sse.c | 455 unsigned imms[2] = {0, 0x3f800000}; local
658 x86_mov_imm(p->func, dst, imms[swizzle[0] - UTIL_FORMAT_SWIZZLE_0]);
668 x86_mov_imm(p->func, x86_make_disp(dst, 4), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]);
686 x86_mov_imm(p->func, x86_make_disp(dst, 8), imms[swizzle[2] - UTIL_FORMAT_SWIZZLE_0]);
696 x86_mov_imm(p->func, x86_make_disp(dst, 12), imms[swizzle[3] - UTIL_FORMAT_SWIZZLE_0]);
714 unsigned imms[2] = {0, 1}; local
773 imms[1] = (output_desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) ? 0xffff : 0x7ffff;
797 x86_mov16_imm(p->func, x86_make_disp(dst, 2), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]);
803 x86_mov_imm(p->func, dst, (imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0] << 16) | imms[swizzl
[all...] |
| /external/vixl/src/a64/ |
| H A D | assembler-a64.cc | 740 unsigned imms) {
744 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
751 unsigned imms) {
755 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
762 unsigned imms) {
766 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1929 // N imms immr size S R
737 bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
748 sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
759 ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) argument
|
| /external/valgrind/main/VEX/priv/ |
| H A D | guest_arm64_toIR.c | 1827 ULong immN, ULong imms, ULong immr, Bool immediate,
1831 vassert(imms < (1ULL << 6));
1836 Int len = dbm_highestSetBit( ((immN << 6) & 64) | ((~imms) & 63) );
1846 if (immediate && ((imms & levels) == levels)) {
1847 /* printf("fail2 imms %llu levels %llu len %d\n", imms, levels, len); */
1851 ULong S = imms & levels;
1979 sf op 100100 N immr imms Rn Rd
2111 sf 10 100110 N immr imms nn dd
2112 UBFM Wd, Wn, #immr, #imms whe
1826 dbm_DecodeBitMasks( ULong* wmask, ULong* tmask, ULong immN, ULong imms, ULong immr, Bool immediate, UInt M ) argument
[all...] |