Searched defs:mask (Results 1 - 21 of 21) sorted by relevance

/art/runtime/arch/arm64/
H A Dmemcmp16_arm64.S45 #define mask x13 define
79 mov mask, #~0
80 lsl mask, mask, limit
81 bic data1, data1, mask
82 bic data2, data2, mask
93 // Create a 16b mask
94 mov mask, #0xFFFF
99 and data1, data1, mask
100 and data2, data2, mask
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/art/compiler/dex/quick/
H A Dresource_mask.cc143 const ResourceMask* ResourceMaskCache::GetMask(const ResourceMask& mask) { argument
151 if ((mask.masks_[0] >> 32) == 0u && (mask.masks_[1] & ~kAllowedSpecialBits.masks_[1]) == 0u) {
153 uint32_t low_regs = static_cast<uint32_t>(mask.masks_[0]);
155 if (low_regs_without_lowest == 0u && IsPowerOfTwo(mask.masks_[1])) {
156 // 0 or 1 register, 0 or 1 bit from kAllowedBits. Use a pre-defined mask.
157 size_t index = (mask.masks_[1] != 0u) ? CLZ(mask.masks_[1]) : 0u;
161 } else if (IsPowerOfTwo(low_regs_without_lowest) && mask.masks_[1] == 0u) {
162 // 2 registers and no other flags. Use predefined mask i
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H A Dmir_to_lir-inl.h143 inline void Mir2Lir::SetupRegMask(ResourceMask* mask, int reg) { argument
146 *mask = mask->Union(reginfo_map_.Get(reg)->DefUseMask());
152 inline void Mir2Lir::ClearRegMask(ResourceMask* mask, int reg) { argument
155 *mask = mask->ClearBits(reginfo_map_.Get(reg)->DefUseMask());
159 * Set up the proper fields in the resource mask
183 /* Set up the mask for resources. */
H A Dralloc_util.cc41 Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask) argument
43 s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this), def_start_(nullptr),
128 // Add an entry for InvalidReg with zero'd mask.
H A Dcodegen_util.cc136 ResourceMask mask; local
142 mask = **mask_ptr;
144 mask.ClearBits(kEncodeMem);
149 mask.SetBit(ResourceMask::kLiteral);
152 mask.SetBit(ResourceMask::kDalvikReg);
155 mask.SetBit(ResourceMask::kHeapRef);
160 mask.SetBit(ResourceMask::kMustNotAlias);
165 *mask_ptr = mask_cache_.GetMask(mask);
/art/disassembler/
H A Ddisassembler_mips.cc29 uint32_t mask; member in struct:art::mips::MipsInstruction
35 return (instruction & mask) == value;
H A Ddisassembler_arm.cc1873 uint32_t mask = opB; local
1878 size_t count = 3 - CTZ(mask);
1882 bool positive_mask = ((mask & (1 << (3 - i))) != 0);
/art/runtime/gc/accounting/
H A Dspace_bitmap-inl.h38 const uword mask = OffsetToMask(offset); local
45 if ((old_word & mask) != 0) {
49 } while (!atomic_entry->CompareExchangeWeakSequentiallyConsistent(old_word, old_word | mask));
164 const uword mask = OffsetToMask(offset); local
169 *address = old_word | mask;
171 *address = old_word & ~mask;
174 return (old_word & mask) != 0;
/art/runtime/
H A Dinstruction_set.h189 explicit InstructionSetFeatures(uint32_t mask) : mask_(mask) {} argument
H A Dstack_map.h176 void SetRegisterMask(uint32_t mask) { argument
177 region_.Store<uint32_t>(kRegisterMaskOffset, mask);
H A Dmem_map.cc90 // mask = 0000111111111110000
111 constexpr uintptr_t mask = mask_ones & ~(kPageSize - 1); local
114 return (input & mask) + LOW_MEM_START;
121 // The lower 8B are taken for the stack guard. Use the upper 8B (with mask).
H A Dstack.cc283 uint64_t mask = 0xffffffff; local
285 mask = mask << 32;
289 new_value = static_cast<uintptr_t>((old_reg_val_as_wide & mask) | new_vreg_portion);
/art/runtime/mirror/
H A Dart_method.h128 uint32_t mask = kAccFastNative | kAccNative; local
129 return (GetAccessFlags() & mask) == mask;
/art/compiler/dex/quick/arm/
H A Dtarget_arm.cc491 void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { argument
495 if (mask.Equals(kEncodeAll)) {
502 if (mask.HasBit(i)) {
508 if (mask.HasBit(ResourceMask::kCCode)) {
511 if (mask.HasBit(ResourceMask::kFPStatus)) {
516 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) {
521 if (mask.HasBit(ResourceMask::kLiteral)) {
525 if (mask.HasBit(ResourceMask::kHeapRef)) {
528 if (mask.HasBit(ResourceMask::kMustNotAlias)) {
588 // Singles should show a single 32-bit mask bi
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H A Dint_arm.cc44 int mask; local
66 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) |
68 return NewLIR2(kThumb2It, code, mask);
72 int mask; local
94 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) |
96 it->operands[1] = mask;
101 // we could check that the number of instructions matches the mask
/art/compiler/dex/quick/mips/
H A Dtarget_mips.cc287 void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, const ResourceMask& mask, const char *prefix) { argument
291 if (mask.Equals(kEncodeAll)) {
298 if (mask.HasBit(i)) {
304 if (mask.HasBit(ResourceMask::kCCode)) {
307 if (mask.HasBit(ResourceMask::kFPStatus)) {
311 if (mips_lir && (mask.HasBit(ResourceMask::kDalvikReg))) {
316 if (mask.HasBit(ResourceMask::kLiteral)) {
320 if (mask.HasBit(ResourceMask::kHeapRef)) {
323 if (mask.HasBit(ResourceMask::kMustNotAlias)) {
455 // Singles should show a single 32-bit mask bi
532 uint32_t mask = core_spill_mask_; local
547 uint32_t mask = core_spill_mask_; local
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/art/compiler/dex/quick/arm64/
H A Dtarget_arm64.cc147 // Check if the shape mask is zero (i.e. invalid).
308 unsigned mask = (unsigned)(width - 1); local
309 DCHECK_NE((imm_s & mask), mask);
310 uint64_t bits = BIT_MASK((imm_s & mask) + 1);
311 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width);
520 void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { argument
524 if (mask.Equals(kEncodeAll)) {
531 if (mask.HasBit(i)) {
537 if (mask
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H A Dutility_arm64.cc257 uint64_t mask = (UINT64_C(1) << (width >> 1)) - 1; local
258 if ((value & mask) == ((value >> (width >> 1)) & mask)) {
/art/runtime/gc/allocator/
H A Drosalloc.cc867 const uint32_t mask = 1U << ffz; local
870 DCHECK_EQ(*alloc_bitmap_ptr & mask, 0U);
871 *alloc_bitmap_ptr |= mask;
872 DCHECK_NE(*alloc_bitmap_ptr & mask, 0U);
908 const uint32_t mask = 1U << vec_off; local
909 DCHECK_NE(*vec & mask, 0U);
910 *vec &= ~mask;
911 DCHECK_EQ(*vec & mask, 0U);
946 // Only not all free if a bit other than the mask bits are set.
1020 const uint32_t mask local
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/art/compiler/utils/arm/
H A Dassembler_thumb2.cc1950 // Convert the given IT state to a mask bit given bit 0 of the first
1985 uint8_t mask = ToItMask(i1, firstcond0, 3); local
1989 mask |= ToItMask(i2, firstcond0, 2);
1992 mask |= ToItMask(i3, firstcond0, 1);
1995 mask |= 0b0001;
2006 mask;
/art/compiler/dex/quick/x86/
H A Dtarget_x86.cc397 void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { argument
401 if (mask.Equals(kEncodeAll)) {
408 if (mask.HasBit(i)) {
414 if (mask.HasBit(ResourceMask::kCCode)) {
418 if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) {
423 if (mask.HasBit(ResourceMask::kLiteral)) {
427 if (mask.HasBit(ResourceMask::kHeapRef)) {
430 if (mask.HasBit(ResourceMask::kMustNotAlias)) {
656 // Singles should show a single 32-bit mask bit, at first referring to the low half.
671 // 32bit W should show a single 32-bit mask bi
696 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); local
713 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); local
729 uint32_t mask = fp_spill_mask_; local
743 uint32_t mask = fp_spill_mask_; local
1622 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); local
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