| /external/elfutils/0.153/libdwfl/ |
| H A D | dwfl_module_register_names.c | 74 int nregs = ebl_register_info (mod->ebl, -1, NULL, 0, local
77 for (int regno = 0; regno < nregs && likely (result == 0); ++regno)
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| /external/elfutils/0.153/backends/ |
| H A D | ia64_retval.c | 100 inline int hfa (const Dwarf_Op *loc, int nregs) argument
106 return fpregs_used + nregs;
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| /external/libunwind/src/ia64/ |
| H A D | Grbs.c | 128 unw_word_t nregs, bsp = c->bsp, curr = c->rbs_curr, n; local
149 nregs = rse_num_regs (bsp, c->rbs_area[curr].end);
151 if (regs_to_skip < nregs)
170 regs_to_skip -= nregs;
199 rbs_cover_and_flush (struct cursor *c, unw_word_t nregs, argument
209 c->bsp = rse_skip_regs (bsp, nregs);
215 if (likely (n >= nregs))
232 nregs -= n; /* account for registers already on the rbs */
234 assert (rse_skip_regs (c->bsp, -nregs) == rse_skip_regs (rbs->end, 0));
239 nregs
[all...] |
| /external/elfutils/0.153/libdw/ |
| H A D | cfi.h | 206 size_t nregs; member in struct:Dwarf_Frame_s
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| /external/jemalloc/src/ |
| H A D | stats.c | 87 uint32_t nregs; local
106 CTL_J_GET("arenas.bin.0.nregs", &nregs, uint32_t);
132 j, reg_size, nregs, run_size / page,
140 j, reg_size, nregs, run_size / page,
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
| H A D | r600.h | 116 unsigned nregs; member in struct:r600_pipe_state
234 state->regs[state->nregs].value = value;
235 state->nregs++;
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| /external/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600.h | 116 unsigned nregs; member in struct:r600_pipe_state
234 state->regs[state->nregs].value = value;
235 state->nregs++;
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| /external/qemu/target-arm/ |
| H A D | op_helper.c | 483 int nregs; member in struct:__anon30112
505 const int nregs = neon_ls_element_type[op].nregs; local
513 for (reg = 0; reg < nregs; reg++) {
514 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
516 } else if (interleave == 2 && nregs == 4 && reg == 2) {
|
| H A D | helper.c | 365 int nregs; local
368 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
369 if (reg < nregs) {
375 nregs += 16;
376 if (reg < nregs) {
382 switch (reg - nregs) {
392 int nregs; local
394 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
395 if (reg < nregs) {
400 nregs
[all...] |
| H A D | translate.c | 3884 int nregs; member in struct:__anon30113
3907 int nregs; local
3947 nregs = neon_ls_element_type[op].nregs;
3956 stride = nregs * 8;
3966 nregs = ((insn >> 8) & 3) + 1;
3969 if (nregs != 4 || a == 0) {
3975 if (nregs == 1 && a == 1 && size == 0) {
3978 if (nregs == 3 && a == 1) {
3983 if (nregs
[all...] |
| /external/jemalloc/include/jemalloc/internal/ |
| H A D | arena.h | 199 /* Index of next region that has never been allocated, or nregs. */
232 * | region nregs-1 |
256 uint32_t nregs; member in struct:arena_bin_info_s
1018 assert(regind < bin_info->nregs);
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| /external/valgrind/main/VEX/priv/ |
| H A D | host_amd64_defs.c | 135 void getAllocableRegs_AMD64 ( Int* nregs, HReg** arr ) argument
138 *nregs = 6;
139 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
149 *nregs = 20;
150 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
813 AMD64Instr* AMD64Instr_A87Free ( Int nregs )
817 i->Ain.A87Free.nregs = nregs;
818 vassert(nregs >= 1 && nregs <
[all...] |
| H A D | host_x86_defs.c | 105 void getAllocableRegs_X86 ( Int* nregs, HReg** arr ) argument
107 *nregs = 20;
108 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
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| H A D | host_amd64_defs.h | 557 /* Do 'ffree' on %st(7) .. %st(7-nregs) */
559 Int nregs; /* 1 <= nregs <= 7 */ member in struct:__anon31681::__anon31682::__anon31707
723 extern AMD64Instr* AMD64Instr_A87Free ( Int nregs );
|
| H A D | host_mips_defs.c | 561 void getAllocableRegs_MIPS(Int * nregs, HReg ** arr, Bool mode64) argument
567 *nregs = 20;
569 *nregs = 28;
571 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
610 vassert(i == *nregs);
|
| H A D | host_arm64_defs.c | 131 void getAllocableRegs_ARM64 ( Int* nregs, HReg** arr ) argument
134 *nregs = 24;
135 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
199 vassert(i == *nregs);
|
| H A D | host_arm_defs.c | 122 void getAllocableRegs_ARM ( Int* nregs, HReg** arr ) argument
125 *nregs = 26;
126 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
187 vassert(i == *nregs);
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| H A D | host_ppc_defs.c | 196 void getAllocableRegs_PPC ( Int* nregs, HReg** arr, Bool mode64 ) argument
200 *nregs = (32-9) + (32-24) + (32-24);
202 *nregs = (32-7) + (32-24) + (32-24);
203 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
270 vassert(i == *nregs);
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| H A D | host_s390_defs.c | 116 s390_hreg_get_allocable(Int *nregs, HReg **arr) argument
121 *nregs = 16 /* GPRs */
130 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
426 getAllocableRegs_S390(Int *nregs, HReg **arr, Bool mode64) argument
428 s390_hreg_get_allocable(nregs, arr);
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| H A D | guest_arm_toIR.c | 8597 // Make 'nregs' be the number of registers and 'regstep'
8600 // Dd, Dd+1 regs = 1, inc = 1, nregs = 2, regstep = 1
8601 // Dd, Dd+2 regs = 1, inc = 2, nregs = 2, regstep = 2
8602 // Dd, Dd+1, Dd+2, Dd+3 regs = 2, inc = 2, nregs = 4, regstep = 1
8603 UInt nregs = 2; local
8610 nregs = 4;
8616 if (nregs == 2) {
8640 vassert(nregs == 4);
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