| /art/compiler/dex/quick/mips/ |
| H A D | utility_mips.cc | 356 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
373 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
375 first = OpRegRegImm(kOpLsl, t_reg, r_index, scale);
409 LIR* MipsMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, argument
425 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
427 first = OpRegRegImm(kOpLsl, t_reg, r_index, scale);
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| /art/compiler/dex/quick/arm/ |
| H A D | utility_arm.cc | 692 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
694 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_dest.Low8();
722 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(),
725 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index);
751 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
753 load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale);
758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, argument
760 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_src.Low8();
789 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(),
792 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index);
[all...] |
| /art/compiler/dex/quick/x86/ |
| H A D | utility_x86.cc | 634 LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, argument
638 bool is_array = r_index.Valid();
716 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
721 if (r_dest.GetHigh() == r_index) {
724 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
726 load2 = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
731 load = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
733 load2 = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
737 if (r_dest.GetLow() == r_index) {
740 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index
761 LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, OpSize size) argument
781 StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_src, OpSize size) argument
865 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
[all...] |
| /art/compiler/dex/quick/arm64/ |
| H A D | utility_arm64.cc | 1024 LIR* Arm64Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
1031 // TODO(Arm64): The sign extension of r_index should be carried out by using an extended
1033 if (r_index.Is32Bit()) {
1035 r_index = As64BitReg(r_index);
1036 NewLIR4(WIDE(kA64Sbfm4rrdd), r_index.GetReg(), r_index.GetReg(), 0, 31);
1052 return NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(),
1097 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
1100 load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index
1107 LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) argument
1112 StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, OpSize size) argument
1187 StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) argument
[all...] |
| /art/compiler/dex/quick/ |
| H A D | mir_to_lir.h | 1008 virtual LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, argument
1010 return LoadBaseIndexed(r_base, r_index, r_dest, scale, kReference);
1036 virtual LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, argument
1038 return StoreBaseIndexed(r_base, r_index, r_src, scale, kReference);
1151 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
1157 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
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