| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | SIRegisterInfo.cpp | 21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
24 TII(tii)
20 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii) argument
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| H A D | AMDGPURegisterInfo.cpp | 20 const TargetInstrInfo &tii)
23 TII(tii)
19 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii) argument
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| H A D | R600RegisterInfo.cpp | 21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
24 TII(tii)
20 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii) argument
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| H A D | AMDILCFGStructurizer.cpp | 1903 const AMDGPUInstrInfo *tii = local
1971 tii->getMovImmInstr(preBranchBlk->getParent(), preValReg,
1977 BuildMI(preBranchBlk, DL, tii->get(tii->getIEQOpcode()), condResReg)
1980 BuildMI(preBranchBlk, DL, tii->get(AMDGPU::BRANCH_COND_i32))
3013 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3015 blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL);
3036 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3038 ->CreateMachineInstr(tii->get(newOpcode), DL);
3050 const TargetInstrInfo *tii local
3068 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3088 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3104 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3119 const AMDGPUInstrInfo *tii = local
3132 const AMDGPUInstrInfo *tii = local
3152 const AMDGPUInstrInfo *tii = local
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | SIRegisterInfo.cpp | 21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
24 TII(tii)
20 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii) argument
|
| H A D | AMDGPURegisterInfo.cpp | 20 const TargetInstrInfo &tii)
23 TII(tii)
19 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii) argument
|
| H A D | R600RegisterInfo.cpp | 21 const TargetInstrInfo &tii)
22 : AMDGPURegisterInfo(tm, tii),
24 TII(tii)
20 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii) argument
|
| H A D | AMDILCFGStructurizer.cpp | 1903 const AMDGPUInstrInfo *tii = local
1971 tii->getMovImmInstr(preBranchBlk->getParent(), preValReg,
1977 BuildMI(preBranchBlk, DL, tii->get(tii->getIEQOpcode()), condResReg)
1980 BuildMI(preBranchBlk, DL, tii->get(AMDGPU::BRANCH_COND_i32))
3013 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3015 blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL);
3036 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3038 ->CreateMachineInstr(tii->get(newOpcode), DL);
3050 const TargetInstrInfo *tii local
3068 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3088 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3104 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local
3119 const AMDGPUInstrInfo *tii = local
3132 const AMDGPUInstrInfo *tii = local
3152 const AMDGPUInstrInfo *tii = local
[all...] |
| /external/llvm/lib/CodeGen/ |
| H A D | Spiller.cpp | 58 const TargetInstrInfo *tii; member in class:__anon25824::SpillerBase
68 tii = mf.getTarget().getInstrInfo();
136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc,
145 tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg,
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| H A D | TargetSchedule.cpp | 56 const TargetInstrInfo *tii) {
59 TII = tii;
54 init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, const TargetInstrInfo *tii) argument
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| H A D | RegAllocPBQP.cpp | 127 const TargetInstrInfo *tii; member in class:__anon25793::RegAllocPBQP
536 tii = tm->getInstrInfo();
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| H A D | BranchFolding.cpp | 183 const TargetInstrInfo *tii,
186 if (!tii) return false;
190 TII = tii;
182 OptimizeFunction(MachineFunction &MF, const TargetInstrInfo *tii, const TargetRegisterInfo *tri, MachineModuleInfo *mmi) argument
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| H A D | MachineScheduler.cpp | 1237 LoadClusterMutation(const TargetInstrInfo *tii, argument
1239 : TII(tii), TRI(tri) {}
1334 MacroFusion(const TargetInstrInfo *tii): TII(tii) {} argument
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 36 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo *tii, argument
38 : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {}
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1646 const TargetInstrInfo *tii,
1651 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(nullptr) {
1766 const TargetInstrInfo *tii,
1770 tii, tri, tli),
1763 RegReductionPriorityQueue(MachineFunction &mf, bool tracksrp, bool srcorder, const TargetInstrInfo *tii, const TargetRegisterInfo *tri, const TargetLowering *tli) argument
|