Searched defs:tile_y (Results 1 - 25 of 29) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
H A Dintel_span.c76 uint32_t tile_y = y / tile_height; local
82 uintptr_t u = tile_y * row_size
H A Dintel_fbo.c579 uint32_t *tile_y)
587 *tile_y = irb->draw_y & mask_y;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dgen7_misc_state.c109 uint32_t tile_x = 0, tile_y = 0; local
120 tile_y = draw_y & tile_mask_y;
129 * We have no guarantee that tile_x and tile_y are correctly aligned,
134 * tile_x and tile_y to 0. This is a temporary workaround until we
138 tile_y &= ~7;
143 ((srb->Base.Base.Height + tile_y - 1) << 18);
152 OUT_BATCH(tile_x | (tile_y << 16));
157 uint32_t tile_x, tile_y, offset; local
162 tile_y = draw_y & tile_mask_y;
171 * We have no guarantee that tile_x and tile_y ar
[all...]
H A Dintel_span.c76 uint32_t tile_y = y / tile_height; local
82 uintptr_t u = tile_y * row_size
H A Dbrw_misc_state.c372 uint32_t tile_x, tile_y; local
399 tile_y = draw_y & tile_mask_y;
408 * We have no guarantee that tile_x and tile_y are correctly aligned,
413 * tile_x and tile_y to 0. This is a temporary workaround until we come
418 tile_y &= ~7;
431 (stencil_irb->Base.Base.Height + tile_y - 1) << 19);
435 OUT_BATCH(tile_x | (tile_y << 16));
437 assert(tile_x == 0 && tile_y == 0);
446 uint32_t tile_x, tile_y, offset; local
457 tile_y
[all...]
H A Dgen7_wm_surface_state.c510 uint32_t tile_x, tile_y; local
552 surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
560 assert(tile_y % 2 == 0);
562 surf->ss5.y_offset = tile_y / 2;
H A Dgen7_blorp.cpp153 uint32_t tile_x, tile_y; local
171 surf->ss1.base_addr = surface->compute_tile_offsets(&tile_x, &tile_y);
178 assert(tile_y % 2 == 0);
180 surf->ss5.y_offset = tile_y / 2;
590 uint32_t tile_y = draw_y & tile_mask_y; local
603 * We have no guarantee that tile_x and tile_y are correctly aligned,
608 * tile_x and tile_y to 0. This is a temporary workaround until we come
612 tile_y &= ~7;
629 (params->depth.height + tile_y - 1) << 18);
632 tile_y << 1
[all...]
H A Dgen6_blorp.cpp427 uint32_t tile_x, tile_y; local
439 surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
462 assert(tile_y % 2 == 0);
464 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
842 uint32_t tile_y = draw_y & tile_mask_y; local
855 * We have no guarantee that tile_x and tile_y are correctly aligned,
860 * tile_x and tile_y to 0. This is a temporary workaround until we come
864 tile_y &= ~7;
885 (params->depth.height + tile_y - 1) << 19);
888 tile_y << 1
[all...]
H A Dintel_fbo.c579 uint32_t *tile_y)
587 *tile_y = irb->draw_y & mask_y;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
H A Dbrw_wm_surface_state.c1125 uint32_t tile_x, tile_y; local
1130 intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1132 if (tile_x != 0 || tile_y != 0) {
1195 surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1206 assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1211 assert(tile_y % 2 == 0);
1213 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/
H A Dintel_span.c76 uint32_t tile_y = y / tile_height; local
82 uintptr_t u = tile_y * row_size
H A Dintel_fbo.c579 uint32_t *tile_y)
587 *tile_y = irb->draw_y & mask_y;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_span.c76 uint32_t tile_y = y / tile_height; local
82 uintptr_t u = tile_y * row_size
H A Dintel_fbo.c579 uint32_t *tile_y)
587 *tile_y = irb->draw_y & mask_y;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dgen7_misc_state.c109 uint32_t tile_x = 0, tile_y = 0; local
120 tile_y = draw_y & tile_mask_y;
129 * We have no guarantee that tile_x and tile_y are correctly aligned,
134 * tile_x and tile_y to 0. This is a temporary workaround until we
138 tile_y &= ~7;
143 ((srb->Base.Base.Height + tile_y - 1) << 18);
152 OUT_BATCH(tile_x | (tile_y << 16));
157 uint32_t tile_x, tile_y, offset; local
162 tile_y = draw_y & tile_mask_y;
171 * We have no guarantee that tile_x and tile_y ar
[all...]
H A Dintel_span.c76 uint32_t tile_y = y / tile_height; local
82 uintptr_t u = tile_y * row_size
H A Dbrw_misc_state.c372 uint32_t tile_x, tile_y; local
399 tile_y = draw_y & tile_mask_y;
408 * We have no guarantee that tile_x and tile_y are correctly aligned,
413 * tile_x and tile_y to 0. This is a temporary workaround until we come
418 tile_y &= ~7;
431 (stencil_irb->Base.Base.Height + tile_y - 1) << 19);
435 OUT_BATCH(tile_x | (tile_y << 16));
437 assert(tile_x == 0 && tile_y == 0);
446 uint32_t tile_x, tile_y, offset; local
457 tile_y
[all...]
H A Dgen7_wm_surface_state.c510 uint32_t tile_x, tile_y; local
552 surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
560 assert(tile_y % 2 == 0);
562 surf->ss5.y_offset = tile_y / 2;
H A Dgen7_blorp.cpp153 uint32_t tile_x, tile_y; local
171 surf->ss1.base_addr = surface->compute_tile_offsets(&tile_x, &tile_y);
178 assert(tile_y % 2 == 0);
180 surf->ss5.y_offset = tile_y / 2;
590 uint32_t tile_y = draw_y & tile_mask_y; local
603 * We have no guarantee that tile_x and tile_y are correctly aligned,
608 * tile_x and tile_y to 0. This is a temporary workaround until we come
612 tile_y &= ~7;
629 (params->depth.height + tile_y - 1) << 18);
632 tile_y << 1
[all...]
H A Dgen6_blorp.cpp427 uint32_t tile_x, tile_y; local
439 surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
462 assert(tile_y % 2 == 0);
464 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
842 uint32_t tile_y = draw_y & tile_mask_y; local
855 * We have no guarantee that tile_x and tile_y are correctly aligned,
860 * tile_x and tile_y to 0. This is a temporary workaround until we come
864 tile_y &= ~7;
885 (params->depth.height + tile_y - 1) << 19);
888 tile_y << 1
[all...]
H A Dintel_fbo.c579 uint32_t *tile_y)
587 *tile_y = irb->draw_y & mask_y;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_span.c76 uint32_t tile_y = y / tile_height; local
82 uintptr_t u = tile_y * row_size
H A Dintel_fbo.c579 uint32_t *tile_y)
587 *tile_y = irb->draw_y & mask_y;
577 intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, uint32_t *tile_y) argument
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/
H A Dlp_rast.c340 const unsigned tile_x = task->x, tile_y = task->y; local
367 tile_x + x, tile_y + y);
370 depth = lp_rast_get_depth_block_pointer(task, tile_x + x, tile_y + y);
375 tile_x + x, tile_y + y,
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_rast.c340 const unsigned tile_x = task->x, tile_y = task->y; local
367 tile_x + x, tile_y + y);
370 depth = lp_rast_get_depth_block_pointer(task, tile_x + x, tile_y + y);
375 tile_x + x, tile_y + y,

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