Searched defs:width0 (Results 1 - 25 of 30) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dradeon_mipmap_tree.h74 GLuint width0; /** Width of baseLevel image */ member in struct:_radeon_mipmap_tree
105 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
H A Dradeon_mipmap_tree.c170 mt->levels[level].width = minify(mt->width0, i);
190 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
204 mt->width0 = width0;
339 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_mipmap_tree.h74 GLuint width0; /** Width of baseLevel image */ member in struct:_radeon_mipmap_tree
105 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
H A Dradeon_mipmap_tree.c170 mt->levels[level].width = minify(mt->width0, i);
190 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
204 mt->width0 = width0;
339 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument
/external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/
H A Dst_texture.h78 GLuint width0, height0, depth0; member in struct:st_texture_object
152 GLuint width0,
H A Dst_texture.c50 * width0, height0, depth0 are the dimensions of the level 0 image
59 GLuint width0,
69 assert(width0 > 0);
86 pt.width0 = width0;
195 if (ptWidth != u_minify(pt->width0, image->Level) ||
317 u_minify(dst->width0, level),
325 u_minify(dst->width0, level),
345 region.x = src->width0 / 2;
374 GLuint width = u_minify(dst->width0, dstLeve
55 st_texture_create(struct st_context *st, enum pipe_texture_target target, enum pipe_format format, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, GLuint layers, GLuint bind ) argument
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H A Dst_cb_texture.c252 GLuint *width0, GLuint *height0, GLuint *depth0)
306 *width0 = width;
343 stObj->width0 = stObj->height0 = stObj->depth0 = 0;
374 stObj->width0 = width;
1132 assert(u_minify(stImage->pt->width0, src_level) == stImage->base.Width);
1225 width = stObj->width0;
1241 stObj->pt->width0 != ptWidth ||
1288 (stImage->base.Width == u_minify(stObj->width0, level) &&
1322 stObj->width0 = width;
250 guess_base_level_size(GLenum target, GLuint width, GLuint height, GLuint depth, GLuint level, GLuint *width0, GLuint *height0, GLuint *depth0) argument
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dradeon_mipmap_tree.h74 GLuint width0; /** Width of baseLevel image */ member in struct:_radeon_mipmap_tree
105 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
H A Dradeon_mipmap_tree.c170 mt->levels[level].width = minify(mt->width0, i);
190 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
204 mt->width0 = width0;
339 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_mipmap_tree.h74 GLuint width0; /** Width of baseLevel image */ member in struct:_radeon_mipmap_tree
105 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
H A Dradeon_mipmap_tree.c170 mt->levels[level].width = minify(mt->width0, i);
190 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
204 mt->width0 = width0;
339 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
188 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument
/external/mesa3d/src/mesa/state_tracker/
H A Dst_texture.h78 GLuint width0, height0, depth0; member in struct:st_texture_object
152 GLuint width0,
H A Dst_texture.c50 * width0, height0, depth0 are the dimensions of the level 0 image
59 GLuint width0,
69 assert(width0 > 0);
86 pt.width0 = width0;
195 if (ptWidth != u_minify(pt->width0, image->Level) ||
317 u_minify(dst->width0, level),
325 u_minify(dst->width0, level),
345 region.x = src->width0 / 2;
374 GLuint width = u_minify(dst->width0, dstLeve
55 st_texture_create(struct st_context *st, enum pipe_texture_target target, enum pipe_format format, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, GLuint layers, GLuint bind ) argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
H A Dr600_blit.c259 unsigned width0; member in struct:texture_orig_info
278 orig->width0 = tex->width0;
290 new_width = util_format_get_nblocksx(tex->format, orig->width0);
293 tex->width0 = new_width;
310 tex->width0 = orig->width0;
390 sbox.width = texture->resource.b.b.width0;
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/intel/
H A Dintel_mipmap_tree.h215 GLuint width0, height0, depth0; /**< Level zero image dimensions */ member in struct:intel_mipmap_tree
221 * If num_samples > 0, then singlesample_width0 is the value that width0
377 GLuint width0,
H A Dintel_mipmap_tree.c80 GLuint width0,
102 mt->width0 = width0;
144 mt->width0,
192 GLuint width0,
231 } else if (width0 >= 64)
236 first_level, last_level, width0,
805 mt->width0,
841 mt->width0,
1035 mt->singlesample_mt->width0,
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
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/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dr600_blit.c259 unsigned width0; member in struct:texture_orig_info
278 orig->width0 = tex->width0;
290 new_width = util_format_get_nblocksx(tex->format, orig->width0);
293 tex->width0 = new_width;
310 tex->width0 = orig->width0;
390 sbox.width = texture->resource.b.b.width0;
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_mipmap_tree.h215 GLuint width0, height0, depth0; /**< Level zero image dimensions */ member in struct:intel_mipmap_tree
221 * If num_samples > 0, then singlesample_width0 is the value that width0
377 GLuint width0,
H A Dintel_mipmap_tree.c80 GLuint width0,
102 mt->width0 = width0;
144 mt->width0,
192 GLuint width0,
231 } else if (width0 >= 64)
236 first_level, last_level, width0,
805 mt->width0,
841 mt->width0,
1035 mt->singlesample_mt->width0,
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/
H A Dr600_blit.c378 info->src.res->width0, info->src.res->height0,
388 unsigned dst_width = u_minify(info->dst.res->width0, info->dst.level);
394 dst_width == info->src.res->width0 &&
434 templ.width0 = info->src.res->width0;
562 unsigned width0; member in struct:texture_orig_info
580 orig->width0 = tex->width0;
592 new_width = util_format_get_nblocksx(tex->format, orig->width0);
595 tex->width0
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/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_blit.c378 info->src.res->width0, info->src.res->height0,
388 unsigned dst_width = u_minify(info->dst.res->width0, info->dst.level);
394 dst_width == info->src.res->width0 &&
434 templ.width0 = info->src.res->width0;
562 unsigned width0; member in struct:texture_orig_info
580 orig->width0 = tex->width0;
592 new_width = util_format_get_nblocksx(tex->format, orig->width0);
595 tex->width0
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
H A Dintel_mipmap_tree.c80 GLuint width0,
102 mt->width0 = width0;
144 mt->width0,
192 GLuint width0,
231 } else if (width0 >= 64)
236 first_level, last_level, width0,
805 mt->width0,
841 mt->width0,
1035 mt->singlesample_mt->width0,
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dintel_mipmap_tree.c80 GLuint width0,
102 mt->width0 = width0;
144 mt->width0,
192 GLuint width0,
231 } else if (width0 >= 64)
236 first_level, last_level, width0,
805 mt->width0,
841 mt->width0,
1035 mt->singlesample_mt->width0,
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
[all...]
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_mipmap_tree.c80 GLuint width0,
102 mt->width0 = width0;
144 mt->width0,
192 GLuint width0,
231 } else if (width0 >= 64)
236 first_level, last_level, width0,
805 mt->width0,
841 mt->width0,
1035 mt->singlesample_mt->width0,
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dintel_mipmap_tree.c80 GLuint width0,
102 mt->width0 = width0;
144 mt->width0,
192 GLuint width0,
231 } else if (width0 >= 64)
236 first_level, last_level, width0,
805 mt->width0,
841 mt->width0,
1035 mt->singlesample_mt->width0,
75 intel_miptree_create_internal(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool for_region, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
187 intel_miptree_create(struct intel_context *intel, GLenum target, gl_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, enum intel_msaa_layout msaa_layout) argument
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