Searched defs:writemask (Results 1 - 25 of 61) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c524 unsigned int writemask,
537 if (!writemask)
542 srcmasks[src] |= writemask;
545 srcmasks[src] |= writemask;
522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
H A Dradeon_rename_regs.c72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
H A Dradeon_compiler.c168 * writemask is honoured.
170 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask) argument
182 inst->U.I.DstReg.WriteMask &= writemask;
H A Dradeon_variable.c38 * Rewrite the index and writemask for the destination register of var
320 unsigned int writemask; local
334 writemask = sub_inst->WriteMask;
337 writemask = sub_inst->OutputWriteMask;
339 writemask = 0;
342 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask,
392 unsigned int writemask = 0; local
394 writemask |= var->Dst.WriteMask;
397 return writemask;
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c524 unsigned int writemask,
537 if (!writemask)
542 srcmasks[src] |= writemask;
545 srcmasks[src] |= writemask;
522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
H A Dradeon_rename_regs.c72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
H A Dradeon_compiler.c168 * writemask is honoured.
170 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask) argument
182 inst->U.I.DstReg.WriteMask &= writemask;
H A Dradeon_variable.c38 * Rewrite the index and writemask for the destination register of var
320 unsigned int writemask; local
334 writemask = sub_inst->WriteMask;
337 writemask = sub_inst->OutputWriteMask;
339 writemask = 0;
342 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask,
392 unsigned int writemask = 0; local
394 writemask |= var->Dst.WriteMask;
397 return writemask;
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_wm_pass1.c42 if (inst->writemask & (1<<i)) {
44 inst->writemask &= ~(1<<i);
50 return inst->writemask;
123 GLuint writemask; local
144 writemask = get_tracked_mask(c, inst);
145 if (!writemask) {
166 read0 = writemask;
180 read0 = writemask;
181 read1 = writemask;
186 read0 = writemask;
[all...]
H A Dbrw_fs_vector_splitting.cpp273 unsigned int writemask; local
280 writemask = 1;
283 writemask = 1 << i;
296 NULL, writemask));
H A Dbrw_wm_pass0.c247 GLuint writemask )
253 if (writemask & (1<<i)) {
259 out->writemask = writemask;
317 GLuint writemask = inst->DstReg.WriteMask; local
341 pass0_set_dst(c, out, inst, writemask);
353 GLuint writemask = inst->DstReg.WriteMask; local
368 if (writemask & (1 << i)) {
H A Dbrw_eu.h90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon14349::__anon14350
184 * \param writemask WRITEMASK_X/Y/Z/W bitfield
194 GLuint writemask )
217 * set swizzle and writemask to W, as the lower bits of subnr will
223 reg.dw1.bits.writemask = writemask;
531 /* If/else instructions break in align16 mode if writemask & swizzle
693 reg.dw1.bits.writemask &= mask;
701 reg.dw1.bits.writemask = mask;
967 GLuint writemask,
[all...]
H A Dbrw_vec4.cpp123 if (!(reg.writemask & (1 << i)))
152 this->writemask = WRITEMASK_XYZW;
169 int writemask)
176 this->writemask = writemask;
195 this->writemask = WRITEMASK_XYZW;
735 if (!(inst->dst.writemask & (1 << i)))
783 if (scan_inst->dst.writemask & (1 << i) &&
853 scan_inst->dst.writemask &= inst->dst.writemask;
168 dst_reg(register_file file, int reg, const glsl_type *type, int writemask) argument
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_wm_pass1.c42 if (inst->writemask & (1<<i)) {
44 inst->writemask &= ~(1<<i);
50 return inst->writemask;
123 GLuint writemask; local
144 writemask = get_tracked_mask(c, inst);
145 if (!writemask) {
166 read0 = writemask;
180 read0 = writemask;
181 read1 = writemask;
186 read0 = writemask;
[all...]
H A Dbrw_fs_vector_splitting.cpp273 unsigned int writemask; local
280 writemask = 1;
283 writemask = 1 << i;
296 NULL, writemask));
H A Dbrw_wm_pass0.c247 GLuint writemask )
253 if (writemask & (1<<i)) {
259 out->writemask = writemask;
317 GLuint writemask = inst->DstReg.WriteMask; local
341 pass0_set_dst(c, out, inst, writemask);
353 GLuint writemask = inst->DstReg.WriteMask; local
368 if (writemask & (1 << i)) {
H A Dbrw_eu.h90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon27760::__anon27761
184 * \param writemask WRITEMASK_X/Y/Z/W bitfield
194 GLuint writemask )
217 * set swizzle and writemask to W, as the lower bits of subnr will
223 reg.dw1.bits.writemask = writemask;
531 /* If/else instructions break in align16 mode if writemask & swizzle
693 reg.dw1.bits.writemask &= mask;
701 reg.dw1.bits.writemask = mask;
967 GLuint writemask,
[all...]
/external/chromium_org/third_party/mesa/src/src/glsl/
H A Dir_builder.cpp49 assign(deref lhs, operand rhs, int writemask) argument
55 NULL, writemask);
/external/mesa3d/src/glsl/
H A Dir_builder.cpp49 assign(deref lhs, operand rhs, int writemask) argument
55 NULL, writemask);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
H A Dsi_state.h61 uint8_t writemask[2]; member in struct:si_state_dsa
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state.h61 uint8_t writemask[2]; member in struct:si_state_dsa
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c327 LLVMValueRef writemask; local
329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
335 mask = LLVMBuildAnd(builder, mask, writemask, "");
337 mask = writemask;
471 * assume a full writemask and then let LLVM optimization passes eliminate
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/
H A Di915_fpc_translate.c322 * Compute flags for saturation and writemask.
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
865 writemask = inst->Dst[0].Register.WriteMask;
867 if (writemask & TGSI_WRITEMASK_Y) {
870 if (writemask & TGSI_WRITEMASK_X)
889 if (writemask & TGSI_WRITEMASK_X) {
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c327 LLVMValueRef writemask; local
329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
335 mask = LLVMBuildAnd(builder, mask, writemask, "");
337 mask = writemask;
471 * assume a full writemask and then let LLVM optimization passes eliminate
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c322 * Compute flags for saturation and writemask.
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
865 writemask = inst->Dst[0].Register.WriteMask;
867 if (writemask & TGSI_WRITEMASK_Y) {
870 if (writemask & TGSI_WRITEMASK_X)
889 if (writemask & TGSI_WRITEMASK_X) {

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